公开(公告)号：US06902993B2

公开(公告)日：2005-06-07

申请号：US10402750

申请日：2003-03-28

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar ,  Prabhuram Gopalan

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar ,  Prabhuram Gopalan

IPC: H01L21/28 ,  H01L21/324 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/4941 ,  H01L21/28052 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/78

Abstract: In one embodiment, a gate of a transistor is formed by performing a first thermal treatment on a silicon layer, forming a metal stack over the silicon layer, and performing a second thermal treatment on the metal stack. The first thermal treatment may be a rapid thermal annealing step, while the second thermal treatment may be a rapid thermal nitridation step. The resulting gate exhibits relatively low interface contact resistance between the silicon layer and the metal stack, and may thus be advantageously employed in high-speed devices.

Abstract translation: 在一个实施例中，通过在硅层上进行第一热处理，在硅层上形成金属堆叠，并在金属堆上进行第二热处理，形成晶体管的栅极。 第一热处理可以是快速热退火步骤，而第二热处理可以是快速热氮化步骤。 所得到的栅极在硅层和金属堆叠之间表现出相对较低的界面接触电阻，因此可有利地用于高速器件中。

公开(公告)号：US06803321B1

公开(公告)日：2004-10-12

申请号：US10313049

申请日：2002-12-06

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar ,  Sundar Narayanan

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar ,  Sundar Narayanan

IPC: H01I21302

CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/31116 ,  H01L21/3185

Abstract: A method of forming a semiconductor structure comprises forming a nitride layer on a stack, and etching the nitride layer to form spacers in contact with sides of the stack. The stack is on a semiconductor substrate, the stack comprises (i) a gate layer, comprising silicon, (ii) a metallic layer, on the gate layer, and (iii) an etch-stop layer, on the metallic layer. The forming is by CVD with a gas comprising SixL2x, L is an amino group, and X is 1 or 2.

Abstract translation: 形成半导体结构的方法包括在叠层上形成氮化物层，并蚀刻氮化物层以形成与堆叠的侧面接触的间隔物。 叠层在半导体衬底上，堆叠包括（i）栅极层，包括硅，（ii）栅极层上的金属层，和（iii）金属层上的蚀刻停止层。 通过CVD形成气体，其中包含SixL2x的气体，L是氨基，X是1或2。

公开(公告)号：US06680516B1

公开(公告)日：2004-01-20

申请号：US10313267

申请日：2002-12-06

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L2976

CPC classification number: H01L21/76897 ,  H01L29/42372

Abstract: A semiconductor structure, comprises a semiconductor substrate, a gate layer on the semiconductor substrate, a metallic layer on the gate layer, and an etch-stop layer on the metallic layer. A distance between the substrate and a top of the etch-stop layer is a gate stack height, and the gate stack height is at most 2700 angstroms. In addition, the etch-stop layer has a thickness of at least 800 angstroms.

Abstract translation: 半导体结构包括半导体衬底，半导体衬底上的栅极层，栅极层上的金属层以及金属层上的蚀刻停止层。 衬底与蚀刻停止层的顶部之间的距离是栅堆叠高度，栅叠层高度至多为2700埃。 此外，蚀刻停止层的厚度至少为800埃。

公开(公告)号：US07018942B1

公开(公告)日：2006-03-28

申请号：US10988813

申请日：2004-11-15

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Alain Blosse ,  Fuad Badrieh

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Alain Blosse ,  Fuad Badrieh

IPC: H01L21/469

CPC classification number: H01L23/5222 ,  H01L21/76837 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

公开(公告)号：US07396773B1

公开(公告)日：2008-07-08

申请号：US10313283

申请日：2002-12-06

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L21/302

CPC classification number: H01L21/32137 ,  C11D7/261 ,  C11D7/263 ,  C11D7/3218 ,  C11D7/3227 ,  C11D11/0047 ,  H01L21/02063 ,  H01L21/02071 ,  H01L21/28247 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136

Abstract: A method of making a semiconductor structure, comprises cleaning a gate stack with a cleaning solution. The gate stack comprises a gate layer, a metallic layer on the gate layer, and a etch-stop layer on the metallic layer. The gate layer is on a semiconductor substrate, the cleaning solution is a non-oxidizing cleaning solution, and the metallic layer comprises an easily oxidized metal.

Abstract translation: 一种制造半导体结构的方法，包括用清洁溶液清洗栅极堆叠。 栅极堆叠包括栅极层，栅极层上的金属层和金属层上的蚀刻停止层。 栅极层位于半导体基板上，清洗液为非氧化性清洗液，金属层由容易氧化的金属构成。

公开(公告)号：US06869850B1

公开(公告)日：2005-03-22

申请号：US10326525

申请日：2002-12-20

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L21/60 ,  H01L29/417 ,  H01L21/336

CPC classification number: H01L21/76897 ,  H01L29/41775 ,  H01L29/41783

Abstract: In one embodiment, a transistor comprises raised structures over a source region and a drain region. The raised source structures may comprise selectively deposited metal, such as selective tungsten. A self-aligned contact structure formed through a dielectric layer may provide an electrical connection between an overlying structure (e.g., an interconnect line) and the source or drain region. The transistor may further comprise a gate stack having a capping layer over a metal.

Abstract translation: 在一个实施例中，晶体管包括在源极区域和漏极区域上的凸起结构。 升高的源结构可以包括选择性沉积的金属，例如选择性钨。 通过电介质层形成的自对准接触结构可以在上覆结构（例如，互连线）和源极或漏极区之间提供电连接。 晶体管还可以包括在金属上具有覆盖层的栅极堆叠。

公开(公告)号：US06841878B1

公开(公告)日：2005-01-11

申请号：US10672895

申请日：2003-09-26

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Alain Blosse ,  Fuad Badrieh

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Alain Blosse ,  Fuad Badrieh

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/32051 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76838

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Abstract translation: 在一个实施例中，钝化层包括低k电介质。 低k电介质有助于降低金属线在最后一个金属电平的电容，这可能刚好低于钝化水平。 在另一个实施例中，金属线相对较厚。 这有助于降低金属线的电阻并导致RC延迟。

公开(公告)号：US08080453B1

公开(公告)日：2011-12-20

申请号：US10186453

申请日：2002-06-28

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823871 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor substrate, a gate layer containing silicon on the semiconductor substrate, a metallic layer on the gate layer, and a nitride layer on the metallic layer. The gate layer contains a P+ region and an N+ region.

Abstract translation: 半导体结构包括半导体衬底，在半导体衬底上含有硅的栅极层，栅极层上的金属层和金属层上的氮化物层。 栅极层包含P +区和N +区。

公开(公告)号：US07256083B1

公开(公告)日：2007-08-14

申请号：US10185646

申请日：2002-06-28

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L21/8238

CPC classification number: H01L21/28247 ,  H01L21/28061 ,  H01L29/4941

Abstract: A method of making a semiconductor structure includes depositing a nitride layer, on a metallic layer, by PECVD. The metallic layer is on a gate layer containing silicon, and the gate layer is on a semiconductor substrate.

Abstract translation: 制造半导体结构的方法包括通过PECVD在金属层上沉积氮化物层。 金属层位于含硅的栅极层上，栅极层位于半导体衬底上。

公开(公告)号：US07189652B1

公开(公告)日：2007-03-13

申请号：US10313048

申请日：2002-12-06

Applicant: Alain Blosse ,  Sundar Narayanan ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Sundar Narayanan ,  Krishnaswamy Ramkumar

IPC: H01L21/302

CPC classification number: H01L21/28247 ,  H01L21/28061

Abstract: A method of forming a semiconductor structure comprises oxidizing a stack, to form sidewall oxide in contact with sides of the stack. The stack is on a semiconductor substrate, the stack includes a gate layer, comprising silicon; a metallic layer, on the gate layer; and an etch-stop layer, on the metallic layer. The sidewall oxide in contact with the metallic layer is thinner than the sidewall oxide in contact with the gate layer.

Abstract translation: 形成半导体结构的方法包括氧化堆叠，以形成与堆叠的侧面接触的侧壁氧化物。 堆叠在半导体衬底上，堆叠包括包含硅的栅极层; 栅极层上的金属层; 和金属层上的蚀刻停止层。 与金属层接触的侧壁氧化物比与栅极层接触的侧壁氧化物薄。