公开(公告)号：US06744080B2

公开(公告)日：2004-06-01

申请号：US10097651

申请日：2002-03-13

申请人： Alain Chantre ,  Helene Baudry ,  Didier Dutartre

发明人： Alain Chantre ,  Helene Baudry ,  Didier Dutartre

IPC分类号： H01L2973

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.

摘要翻译： 晶体管和双晶硅异质结基极型双极晶体管的制造方法，其中具有SiGe异质结的半导体层通过非选择性外延在衬底的有源区和围绕有源区的绝缘区形成。 在有源区域的一部分上方的半导体层上形成至少一个阻挡层。 在半导体层和停止层的一部分上形成多晶硅层和上绝缘层，留下发射器窗口。 发射极区域通过在发射极窗中外延形成，部分地搁置在上绝缘层上并与半导体层接触。

公开(公告)号：US06656812B1

公开(公告)日：2003-12-02

申请号：US09717825

申请日：2000-11-21

申请人： Michel Marty ,  Didier Dutartre ,  Alain Chantre ,  Sébastien Jouan ,  Pierre Llinares

发明人： Michel Marty ,  Didier Dutartre ,  Alain Chantre ,  Sébastien Jouan ,  Pierre Llinares

IPC分类号： H01L21331

CPC分类号： H01L29/0895

摘要： A vertical bipolar transistor includes a semiconductor substrate, an extrinsic collector layer in the semiconductor substrate, an intrinsic collector on the extrinsic collector, a lateral isolating region surrounding an upper part of the intrinsic collector, an offset extrinsic collector well, a base including a semiconductor region above the intrinsic collector and above the lateral isolating region including at least one silicon layer, and a doped emitter surrounded by the base. The doped emitter may include first and second parts. The first part may be formed from single-crystal silicon and in direct contact with the upper surface of the semiconductor region in a predetermined window in the upper surface above the intrinsic collector. The second part may be formed from polycrystalline silicon. The two parts of the emitter may be separated by a separating oxide layer spaced apart from the emitter-base junction of the transistor.

摘要翻译： 垂直双极晶体管包括半导体衬底，半导体衬底中的非本征集电极层，非本征集电极上的本征集电极，围绕本征集电极的上部的横向隔离区，偏移的外在集电极阱，包括半导体 在包含至少一个硅层的横向隔离区域上方以及由该基极包围的掺杂发射极之上。 掺杂发射器可以包括第一和第二部分。 第一部分可以由单晶硅形成，并且在本征收集器上方的上表面中的预定窗口中与半导体区域的上表面直接接触。 第二部分可以由多晶硅形成。 发射极的两个部分可以通过与晶体管的发射极 - 基极结间隔开的分离氧化物层来分离。

公开(公告)号：US06642096B2

公开(公告)日：2003-11-04

申请号：US09947190

申请日：2001-09-05

申请人： Didier Dutartre ,  Alain Chantre ,  Michel Marty ,  Sébastien Jouan

发明人： Didier Dutartre ,  Alain Chantre ,  Michel Marty ,  Sébastien Jouan

IPC分类号： H01L218249

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/66272

摘要： A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

公开(公告)号：US06472262B2

公开(公告)日：2002-10-29

申请号：US09817898

申请日：2001-03-26

申请人： Alain Chantre ,  Didier Dutartre ,  Hélène Baudry

发明人： Alain Chantre ,  Didier Dutartre ,  Hélène Baudry

IPC分类号： H01L218249

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A self-aligned double-polysilicon type bi-polar transistor with a heterojunction base comprises a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating the intrinsic base region of the transistor. An emitter region situated above the active region and coming into contact with the upper surface of the semiconducting heterojunction region. A polysilicon layer forming the extrinsic base region of the transistor, situated on each side of the emitter region and separated from the semiconducting heterojunction region by a separation layer comprising an electrically conducting connection part situated just outside the emitter region. This connection part ensures an electrical contact between the extrinsic base and the intrinsic base.

摘要翻译： 具有异质结基底的自对准双多晶硅型双极晶体管包括位于半导体衬底的有源区上方的半导体异质结区域和界定有源区域的隔离区域，以及掺入晶体管的本征基极区域。 位于有源区上方并与半导体异质结区的上表面接触的发射极区。 形成晶体管的非本征基极区域的多晶硅层，位于发射极区域的每一侧，并且通过分离层与半导体异质结区域分离，所述分离层包括位于发射极区域正前方的导电连接部分。 该连接部件确保外部基座和内部基座之间的电接触。

公开(公告)号：US06177717B1

公开(公告)日：2001-01-23

申请号：US09323418

申请日：1999-06-01

申请人： Alain Chantre ,  Michel Marty ,  Didier Dutartre ,  Augustin Monroy ,  Michel Laurens ,  Francois Guette

发明人： Alain Chantre ,  Michel Marty ,  Didier Dutartre ,  Augustin Monroy ,  Michel Laurens ,  Francois Guette

IPC分类号： H01L27082

CPC分类号： H01L29/66242 ,  H01L29/0826 ,  H01L29/7378

摘要： The intrinsic collector of a vertical bipolar transitor is grown epitaxially on an extrinsic collector layer buried in a semiconductor substrate. A lateral isolation region surrounds the upper part of the intrinsic collector and an offset extrinsic collector well is produced. An SiGe heterojunction base lying above the intrinsic collector and above the lateral isolation region is produced by non-selective epitaxy. An in-situ doped emitter is produced by epitaxy on a predetermined window in the surface of the base which lies above the intrinsic collector so as to obtain, at least above the window, an emitter region formed from single-crystal silicon and directly in contact with the silicon of the base.

摘要翻译： 垂直双极性偏转器的本征集电极外延生长在埋在半导体衬底中的非本征集电极层上。 横向隔离区域围绕本征收集器的上部，并产生偏移的外部收集阱。 通过非选择性外延生产位于本征收集器之上和横向隔离区上方的SiGe异质结基底。 原位掺杂的发射体通过在位于本征集电极上方的基底表面上的预定窗口上外延生长，以便至少在窗口上方获得由单晶硅形成并直接接触的发射极区域 与基底的硅。

公开(公告)号：US07892927B2

公开(公告)日：2011-02-22

申请号：US11725160

申请日：2007-03-16

申请人： Stephane Monfray ,  Thomas Skotnicki ,  Didier Dutartre ,  Alexandre Talbot

发明人： Stephane Monfray ,  Thomas Skotnicki ,  Didier Dutartre ,  Alexandre Talbot

IPC分类号： H01L21/336

CPC分类号： H01L29/78684 ,  H01L29/66628 ,  H01L29/66772

摘要： A transistor including a germanium-rich channel. The germanium-rich channel is produced by oxidation of the silicon contained in the silicon-germanium intermediate layer starting from the lower surface of the said intermediate layer. The germanium atoms are therefore caused to migrate towards the upper surface of the silicon-germanium intermediate layer, and are stopped by the gate insulating layer. The migration of the atoms during the oxidation step is thus less prejudicial to the performance of the transistor, since the gate insulator of the transistor has already been produced and is not modified during this step. The migration of the germanium atoms towards the gate insulator, which is immobile, leads to a limitation of the surface defects between the channel and the insulator.

摘要翻译： 包括富含锗的通道的晶体管。 通过从所述中间层的下表面开始的硅 - 锗中间层中包含的硅的氧化产生富锗的通道。 因此锗原子迁移到硅 - 锗中间层的上表面，并被栅极绝缘层阻挡。 因此，在氧化步骤期间原子的迁移对晶体管的性能的影响较小，因为晶体管的栅极绝缘体已经被制造并且在该步骤期间不被修改。 锗原子向固定的栅极绝缘体的迁移导致通道和绝缘体之间的表面缺陷的限制。

公开(公告)号：US20070190754A1

公开(公告)日：2007-08-16

申请号：US11704638

申请日：2007-02-09

申请人： Didier Dutartre ,  Nicolas Loubet ,  Alexandre Talbot

发明人： Didier Dutartre ,  Nicolas Loubet ,  Alexandre Talbot

IPC分类号： H01L21/20

CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639

摘要： A method for forming a single-crystal semiconductor layer portion above a hollowed area, including growing by selective epitaxy on an active single-crystal semiconductor region a sacrificial single-crystal semiconductor layer and a single-crystal semiconductor layer, and removing the sacrificial layer. The epitaxial growth is performed while the active region is surrounded with a raised insulating layer and the removal of the sacrificial single-crystal semiconductor layer is performed through an access resulting from an at least partial removal of the raised insulating layer.

摘要翻译： 一种用于在中空区域上方形成单晶半导体层部分的方法，包括通过牺牲单晶半导体层和单晶半导体层在活性单晶半导体区域上的选择性外延生长，以及去除牺牲层。 在有源区域被凸起的绝缘层围绕的同时进行外延生长，并且通过由至少部分去除凸起的绝缘层获得的访问来执行牺牲单晶半导体层的去除。

公开(公告)号：US06642108B2

公开(公告)日：2003-11-04

申请号：US10273925

申请日：2002-10-18

申请人： Thomas Skotnicki ,  Didier Dutartre ,  Pascal Ribot ,  Maryse Paoli ,  Richard Fournel

发明人： Thomas Skotnicki ,  Didier Dutartre ,  Pascal Ribot ,  Maryse Paoli ,  Richard Fournel

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42336

摘要： A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.

公开(公告)号：US06218723B1

公开(公告)日：2001-04-17

申请号：US09390862

申请日：1999-09-03

申请人： Philippe Delpech ,  Etienne Robilliart ,  Didier Dutartre

发明人： Philippe Delpech ,  Etienne Robilliart ,  Didier Dutartre

IPC分类号： H01L2943

CPC分类号： H01L28/40

摘要： A capacitor integrated on a silicon substrate includes a first electrode made of highly doped polysilicon, a thin silicon oxide layer, a second electrode made of polysilicon and a silicide layer covering the second electrode. The second electrode has a high dopant concentration at its interface with the silicon oxide layer and a low or medium dopant concentration at its interface with the silicide layer.

摘要翻译： 集成在硅衬底上的电容器包括由高掺杂多晶硅制成的第一电极，薄氧化硅层，由多晶硅制成的第二电极和覆盖第二电极的硅化物层。 第二电极在其与氧化硅层的界面处具有高掺杂剂浓度，并且在其与硅化物层的界面处具有低或中等掺杂剂浓度。

公开(公告)号：US6132806A

公开(公告)日：2000-10-17

申请号：US106571

申请日：1998-06-29

申请人： Didier Dutartre

发明人： Didier Dutartre

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  C23C16/24

CPC分类号： H01L29/4966 ,  H01L21/2807

摘要： The present invention relates to a method of formation of an Si.sub.1-x Ge.sub.x MOS transistor gate where x is higher than 50%, on an silicon oxide gate insulator layer, consisting of depositing an Si.sub.1-y Ge.sub.y layer of thickness lower than 10 nm, where 0 50%. The desired thickness ranges, for example, between 20 nm and 200 nm. x and z range, for example, between 80% and 90%.

摘要翻译： 本发明涉及一种在氧化硅栅极绝缘体层上形成x高于50％的Si1-xGex MOS晶体管栅极的方法，该方法包括沉积厚度低于10nm的Si1-yGey层，其中0 50％。 期望的厚度范围例如在20nm和200nm之间。 x和z范围，例如在80％和90％之间。