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    Method and system for bypassing a fill buffer located along a first instruction path
    7.
    发明授权
    Method and system for bypassing a fill buffer located along a first instruction path 有权
    绕过位于第一条指令路径的填充缓冲区的方法和系统

    公开(公告)号：US06442674B1

    公开(公告)日：2002-08-27

    申请号：US09223297

    申请日：1998-12-30

    申请人： Chan Lee ,  Hitesh Ahuja ,  Robert F. Krick

    发明人： Chan Lee ,  Hitesh Ahuja ,  Robert F. Krick

    IPC分类号： G06F9315

    CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/3808

    摘要： A method and system for reducing a latency of microprocessor instructions in transit along an instruction pipeline of a microprocessor by bypassing, at certain times, a fill buffer located between an instruction source and a trace cache unit on the instruction pipeline. The signal path through the fill buffer to the trace cache unit represent a first signal path. In the instruction pipeline, a second signal path is also provided, one which also leads instructions to the trace cache unit, not through the fill buffer, but through a latch provided on the second instruction path. If the latch is enabled, a set of instructions appearing at the input of the fill buffer is transmitted through the latch along the second instruction path and to the trace cache. As a result, the fill buffer is bypassed and a reduced latency for the bypassed instructions is achieved along the instruction pipeline.

    摘要翻译： 一种方法和系统，用于通过在特定时间绕过位于指令流水线上的指令源和跟踪高速缓存单元之间的填充缓冲器来减少沿着微处理器的指令流水线传送的微处理器指令的等待时间。 通过填充缓冲器到跟踪缓存单元的信号路径表示第一信号路径。 在指令流水线中，还提供第二信号路径，其中一个信号路径也不通过填充缓冲器，而是经由设置在第二指令路径上的锁存器将指令引导到跟踪高速缓存单元。 如果锁存器被使能，则出现在填充缓冲器的输入端的一组指令沿着第二指令路径通过锁存器传送到跟踪缓存。 结果，溢出缓冲器被旁路，并且沿着指令流水线实现了绕过指令的降低的等待时间。

    Multi-tag system and method for cache read/write
    8.
    发明授权
    Multi-tag system and method for cache read/write 失效
    多标签系统和缓存读/写方法

    公开(公告)号：US06493797B1

    公开(公告)日：2002-12-10

    申请号：US09540431

    申请日：2000-03-31

    申请人： Chan Lee ,  Richard A. Weier ,  Robert F. Krick

    发明人： Chan Lee ,  Richard A. Weier ,  Robert F. Krick

    IPC分类号： G06F1200

    CPC分类号： G06F9/3808 ,  G06F9/3802 ,  G06F12/0864 ,  Y02D10/13

    摘要： A method and device are provided for reading data from a trace cache in a manner that reduces the time and power consumed by such an operation. A mini-tag is provided for comparing to a requested address to reduce the amount of data that must be read. Mini-tag read and compare operations may be performed in parallel to a full tag read operation, and a data read operation of only the data identified by a matching mini-tag may be performed in parallel to a full tag compare operation. A victim selection method for writing data into the trace cache is used to maintain the uniqueness of the mini-tags.

    摘要翻译： 提供一种方法和装置，用于以减少这种操作消耗的时间和功率的方式从跟踪缓存读取数据。 提供了一个迷你标签，用于与所请求的地址进行比较，以减少必须读取的数据量。 微标签读取和比较操作可以与全标签读取操作并行地执行，并且可以并行地执行与标签对照操作并行的只有由匹配的微型标签识别的数据的数据读取操作。 用于将数据写入跟踪缓存的受害者选择方法用于维护迷你标签的唯一性。

    Processor instruction pipeline with error detection scheme
    9.
    发明授权
    Processor instruction pipeline with error detection scheme 有权
    具有错误检测方案的处理器指令流水线

    公开(公告)号：US06457119B1

    公开(公告)日：2002-09-24

    申请号：US09360192

    申请日：1999-07-23

    申请人： Darrell Boggs ,  Robert F. Krick ,  Chan Lee

    发明人： Darrell Boggs ,  Robert F. Krick ,  Chan Lee

    IPC分类号： G06F938

    CPC分类号： G06F9/3865 ,  G06F9/3842 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/1405

    摘要： Briefly, in accordance with one embodiment of the invention, a processor includes: a multiple unit instruction pipeline. An instruction pipeline includes a microcode source. The microcode source includes the capability of detecting the occurrence of at least one corrupted microcode instruction. The microcode source is also capable of signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. Briefly, in accordance with another embodiment of the invention, a method of executing microcode instructions includes the following. The existence of at least one corrupted microcode instruction is detected and the occurrence of at least one corrupted microcode instruction is signaled. Briefly, in accordance with one more embodiment of the invention, a system includes: a processor with a microcode source capable of detecting the occurrence of at least one corrupted microcode instruction and signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. The system employing the processor further includes main memory, a video card, a system bus, and bulk storage capability.

    摘要翻译： 简而言之，根据本发明的一个实施例，处理器包括：多单元指令流水线。 指令流水线包括微码源。 微代码源包括检测至少一个损坏的微代码指令的发生的能力。 微代码源还能够向至少一个其他指令流水线单元发出至少一个损坏的微代码指令的发生。 简而言之，根据本发明的另一个实施例，执行微码指令的方法包括以下。 检测到存在至少一个损坏的微代码指令，并发出至少一个损坏的微代码指令的发生。 简而言之，根据本发明的另一实施例，一种系统包括：具有微码源的处理器，其能够检测至少一个损坏的微代码指令的发生，并向至少一个其他信号发送至少一个损坏的微代码指令的发生 指令流水线单元。 采用处理器的系统还包括主存储器，视频卡，系统总线和批量存储能力。

    Polyolefin-based thermoplastic polymer composition
    10.
    发明申请
    Polyolefin-based thermoplastic polymer composition 有权
    聚烯烃类热塑性聚合物组合物

    公开(公告)号：US20060183864A1

    公开(公告)日：2006-08-17

    申请号：US11312051

    申请日：2005-12-20

    申请人： Yang Jin ,  Seong Park ,  Chang Jin ,  Chan Lee ,  Se Cho

    发明人： Yang Jin ,  Seong Park ,  Chang Jin ,  Chan Lee ,  Se Cho

    IPC分类号： C08L23/04

    CPC分类号： C08F255/02 ,  C08F285/00 ,  C08L23/02 ,  C08L23/08 ,  C08L23/0869 ,  C08L23/10 ,  C08L33/04 ,  C08L2205/02 ,  C08F220/10 ,  C08L2666/02 ,  C08L2666/06

    摘要： Disclosed herein is a polyolefin-based thermoplastic polymer composition, in which an acrylate copolymer phase obtained by absorbing an alkyl acrylate monomer, an alkyl methacrylate monomer, a polar group-containing acrylate monomer and a polymerization initiator into a polyolefin matrix and then polymerizing the monomers is dispersed in a polyolefin phase. The thermoplastic polymer composition has excellent surface polarity leading to excellent paint adhesion.

    摘要翻译： 本文公开了一种聚烯烃基热塑性聚合物组合物，其中通过将丙烯酸烷基酯单体，甲基丙烯酸烷基酯单体，含极性基团的丙烯酸酯单体和聚合引发剂吸收到聚烯烃基质中，然后使单体聚合而获得的丙烯酸酯共聚物相 分散在聚烯烃相中。 热塑性聚合物组合物具有优异的表面极性，导致优异的涂料附着力。