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    Method and system for bypassing a fill buffer located along a first instruction path
    7.
    发明授权
    Method and system for bypassing a fill buffer located along a first instruction path 有权
    绕过位于第一条指令路径的填充缓冲区的方法和系统

    公开(公告)号：US06442674B1

    公开(公告)日：2002-08-27

    申请号：US09223297

    申请日：1998-12-30

    申请人： Chan Lee ,  Hitesh Ahuja ,  Robert F. Krick

    发明人： Chan Lee ,  Hitesh Ahuja ,  Robert F. Krick

    IPC分类号： G06F9315

    CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/3808

    摘要： A method and system for reducing a latency of microprocessor instructions in transit along an instruction pipeline of a microprocessor by bypassing, at certain times, a fill buffer located between an instruction source and a trace cache unit on the instruction pipeline. The signal path through the fill buffer to the trace cache unit represent a first signal path. In the instruction pipeline, a second signal path is also provided, one which also leads instructions to the trace cache unit, not through the fill buffer, but through a latch provided on the second instruction path. If the latch is enabled, a set of instructions appearing at the input of the fill buffer is transmitted through the latch along the second instruction path and to the trace cache. As a result, the fill buffer is bypassed and a reduced latency for the bypassed instructions is achieved along the instruction pipeline.

    摘要翻译： 一种方法和系统，用于通过在特定时间绕过位于指令流水线上的指令源和跟踪高速缓存单元之间的填充缓冲器来减少沿着微处理器的指令流水线传送的微处理器指令的等待时间。 通过填充缓冲器到跟踪缓存单元的信号路径表示第一信号路径。 在指令流水线中，还提供第二信号路径，其中一个信号路径也不通过填充缓冲器，而是经由设置在第二指令路径上的锁存器将指令引导到跟踪高速缓存单元。 如果锁存器被使能，则出现在填充缓冲器的输入端的一组指令沿着第二指令路径通过锁存器传送到跟踪缓存。 结果，溢出缓冲器被旁路，并且沿着指令流水线实现了绕过指令的降低的等待时间。

    Method and apparatus for decompressing relative addresses
    8.
    发明授权
    Method and apparatus for decompressing relative addresses 失效
    用于解压缩相对地址的方法和装置

    公开(公告)号：US07617382B1

    公开(公告)日：2009-11-10

    申请号：US11197805

    申请日：2005-08-04

    申请人： Bret L. Toll ,  Michael J. St. Clair ,  John A. Miller ,  Hitesh Ahuja

    发明人： Bret L. Toll ,  Michael J. St. Clair ,  John A. Miller ,  Hitesh Ahuja

    IPC分类号： G06F9/26 ,  G06F9/34

    CPC分类号： G06F9/322 ,  G06F9/30003 ,  G06F9/30054 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30178 ,  G06F9/324 ,  G06F9/342 ,  G06F9/3557 ,  G06F9/383

    摘要： A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed relative address is reconstructed from the compressed relative address and an instruction pointer (IP) address associated with the head of the micro-operation storage line in which the compressed relative address was stored. IP-relative addresses may be computed in a manner similar to relative branch targets, then compressed and stored in one or more micro-operation entries of a micro-operation storage line to be reconstructed later according to an IP address associated with the respective micro-operation storage line in which their compressed counterpart was stored.

    摘要翻译： 一种用于解压缩相对地址的方法和装置。 从微操作存储器的一个或多个微操作条目检索压缩的相对地址，并且从压缩的相对地址和与微操作存储器的头部相关联的指令指针（IP）地址重构未压缩的相对地址 存储压缩相对地址的行。 可以以与相对分支目标相似的方式计算IP相对地址，然后压缩并存储在稍后将根据与相应微控制器相关联的IP地址重构的微操作存储线的一个或多个微操作条目中， 存储其压缩对方的操作存储线。

    Method and apparatus for compressing relative addresses
    9.
    发明授权
    Method and apparatus for compressing relative addresses 失效
    用于压缩相对地址的方法和装置

    公开(公告)号：US07111148B1

    公开(公告)日：2006-09-19

    申请号：US10185895

    申请日：2002-06-27

    申请人： Bret L. Toll ,  Michael J. St. Clair ,  John Allan Miller ,  Hitesh Ahuja

    发明人： Bret L. Toll ,  Michael J. St. Clair ,  John Allan Miller ,  Hitesh Ahuja

    IPC分类号： G06F9/26

    CPC分类号： G06F9/322 ,  G06F9/30003 ,  G06F9/30054 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30178

    摘要： A method and apparatus for compressing relative addresses and for storage of compressed relative addresses. A relative virtual address is computed in a particular stage of a processor pipeline and then compressed according to one or more compression techniques for storage in a micro-operation storage. A compressed relative address is retrieved from one or more micro-operation entries of the micro-operation storage and an uncompressed virtual address is reconstructed from the compressed relative address and an instruction pointer (IP) address associated with the head of the micro-operation storage line in which the compressed relative address was stored. IP-relative addresses may be computed in a manner similar to relative branch targets, then compressed and stored in one or more micro-operation entries of a micro-operation storage line to be reconstructed later according to an IP address associated with the respective micro-operation storage line in which their compressed counterpart was stored.

    摘要翻译： 一种用于压缩相对地址和用于存储压缩相对地址的方法和装置。 在处理器流水线的特定阶段中计算相对虚拟地址，然后根据用于存储在微操作存储器中的一种或多种压缩技术进行压缩。 从微操作存储器的一个或多个微操作条目检索压缩的相对地址，并且从压缩的相对地址和与微操作存储器的头部相关联的指令指针（IP）地址重构未压缩的虚拟地址 存储压缩相对地址的行。 可以以与相对分支目标相似的方式计算IP相对地址，然后压缩并存储在稍后将根据与相应微控制器相关联的IP地址重构的微操作存储线的一个或多个微操作条目中， 存储其压缩对方的操作存储线。