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15 条记录 (耗时 0.043 秒)

    Integrated modem and line-isolation circuitry with HDLC framing and associated method
    3.
    发明授权
    Integrated modem and line-isolation circuitry with HDLC framing and associated method 失效
    集成调制解调器和线路隔离电路，具有HDLC框架和相关方法

    公开(公告)号：US07020187B1

    公开(公告)日：2006-03-28

    申请号：US09480747

    申请日：2000-01-10

    申请人： Mitchell Reid ,  Timothy J. Dupuis

    发明人： Mitchell Reid ,  Timothy J. Dupuis

    IPC分类号： H04B1/38 ,  H04L5/16

    CPC分类号： H04M11/066

    摘要： An improved modem architecture and associated method that integrates modem and line-isolation circuitry so as to achieve modem functionality and system-side isolation functionality on a single integrated circuit while also providing a modem interface that allows synchronous modem transmission protocols to be implemented through an asynchronous serial interface is disclosed. For example, one such type of synchronous modem transmission protocol is the HDLC (high-level data link control) protocol. According to the techniques disclosed herein, data and control information of an HDLC protocol may be presented at transmit and receive pins of a modem/system side DAA through an UART even though the UART may be an asynchronous serial receiver transmitter. Thus, both transmit and receive data transfers of a serial modem protocol may be implemented through an asynchronous serial interface.

    摘要翻译： 一种改进的调制解调器架构和相关方法，集成了调制解调器和线路隔离电路，以便在单个集成电路上实现调制解调器功能和系统侧隔离功能，同时还提供调制解调器接口，允许通过异步实现同步调制解调器传输协议 串行接口被公开。 例如，这种类型的同步调制解调器传输协议是HDLC（高级数据链路控制）协议。 根据本文公开的技术，HDLC协议的数据和控制信息可以通过UART在调制解调器/系统侧DAA的发送和接收引脚处呈现，即使UART可以是异步串行接收发射机。 因此，可以通过异步串行接口来实现串行调制解调器协议的发送和接收数据传输。

    Integrated modem and line-isolation circuitry with data flow control and associated method
    4.
    发明授权
    Integrated modem and line-isolation circuitry with data flow control and associated method 失效
    集成调制解调器和线路隔离电路，具有数据流控制和相关方法

    公开(公告)号：US06735246B1

    公开(公告)日：2004-05-11

    申请号：US09479486

    申请日：2000-01-10

    申请人： Timothy J. Dupuis ,  Andrew W. Krone ,  Mitchell Reid

    发明人： Timothy J. Dupuis ,  Andrew W. Krone ,  Mitchell Reid

    IPC分类号： H04L516

    CPC分类号： H04L25/4927 ,  H04L25/0266 ,  H04L27/00

    摘要： An improved modem architecture and associated method are disclosed that integrate modem functionality and line-side isolation functionality while also providing flow control of internal data between an isolation interface, digital-signal-processor (DSP) circuitry, and an analog input. The integrated modem and line-isolation circuit may also have an analog output for which data flow control is also provided.

    摘要翻译： 公开了一种改进的调制解调器架构和相关联的方法，其集成调制解调器功能和线路侧隔离功能，同时还提供隔离接口，数字信号处理器（DSP）电路和模拟输入之间的内部数据的流量控制。 集成的调制解调器和线路隔离电路也可以具有也提供数据流控制的模拟输出。

    Direct digital frequency synthesizer with phase error correction, method therefor, and receiver using same
    5.
    发明授权
    Direct digital frequency synthesizer with phase error correction, method therefor, and receiver using same 失效
    具有相位误差校正的直接数字频率合成器，其方法和使用其的接收机

    公开(公告)号：US07889812B2

    公开(公告)日：2011-02-15

    申请号：US11442195

    申请日：2006-05-26

    申请人： David S. Trager ,  Mitchell Reid

    发明人： David S. Trager ,  Mitchell Reid

    IPC分类号： H03K9/00 ,  H03D3/00 ,  H03M1/66

    CPC分类号： G06F1/0353 ,  G06F1/0335 ,  G06F1/0342

    摘要： A receiver (1000) includes a direct digital frequency synthesizer (DDFS) (700) and first (1040) and second (1042) mixers. The DDFS (700) has a first output for providing a first local oscillator signal, and a second output for providing a second local oscillator signal offset from a quadrature relationship with the first local oscillator signal by a phase offset. The first mixer (1040) has a first input for receiving a radio frequency (RF) signal, a second input for receiving the first local oscillator signal, and an output for providing an in-phase signal at another frequency. The second mixer (1042) has a first input for receiving the RF signal, a second input for receiving the second local oscillator signal, and an output for providing a quadrature signal at the other frequency. The DDFS (700) may be implemented using first (702) and second (704) memories storing portions of a sinusoidal waveform and extra memories (706, 708) supporting the phase offset.

    摘要翻译： 接收器（1000）包括直接数字频率合成器（DDFS）（700）和第一（1040）和第二（1042）混频器。 DDFS（700）具有用于提供第一本地振荡器信号的第一输出和用于提供与第一本地振荡器信号的正交关系偏移相位偏移的第二本地振荡器信号的第二输出。 第一混频器（1040）具有用于接收射频（RF）信号的第一输入端，用于接收第一本机振荡器信号的第二输入端和用于提供另一频率的同相信号的输出端。 第二混频器（1042）具有用于接收RF信号的第一输入端，用于接收第二本机振荡器信号的第二输入端和用于以另一频率提供正交信号的输出端。 DDFS（700）可以使用存储正弦​​波形的部分的第一（702）和第二（704）存储器以及支持相位偏移的额外存储器（706,708）来实现。

    Techniques for performing gain and phase correction in a complex radio frequency receiver
    6.
    发明授权
    Techniques for performing gain and phase correction in a complex radio frequency receiver 失效
    在复杂射频接收机中执行增益和相位校正的技术

    公开(公告)号：US07643600B2

    公开(公告)日：2010-01-05

    申请号：US11565499

    申请日：2006-11-30

    申请人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

    发明人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

    IPC分类号： H04L25/40 ,  H04L7/00 ,  H04L25/00

    CPC分类号： H04L27/3863 ,  H03C3/40

    摘要： A receiver (300) includes a first mixing digital-to-analog converter (DAC) (336, 332), a second mixing DAC (338, 334), a direct digital frequency synthesizer (DDFS) (302), a phase correction circuit (340), a selectable load (306) and a magnitude correction circuit (350). The first mixing DAC (336, 332) includes a first input for receiving an input signal, a second input for receiving a digital first local oscillator (LO) signal and an output. The second mixing DAC (338, 334) includes a first input for receiving the input signal, a second input for receiving a digital second local oscillator (LO) signal and an output. The DDFS (302) is configured to provide the first and second LO signals, which are quadrature signals. The phase correction circuit (340) is configured to provide a phase correction signal to a control input of the DDFS (302). The first selectable load (306) includes an input coupled to the output of the first mixing DAC (336, 332) and a control input. The magnitude correction circuit (350) is configured to provide a first magnitude correction signal to the control input of the first selectable load (306).

    摘要翻译： 接收器（300）包括第一混合数模转换器（DAC）（336,332），第二混合DAC（338,334），直接数字频率合成器（DDFS）（302），相位校正电路 （340），可选负载（306）和幅度校正电路（350）。 第一混合DAC（336,332）包括用于接收输入信号的第一输入端，用于接收数字第一本地振荡器（LO）信号和输出的第二输入端。 第二混合DAC（338,334）包括用于接收输入信号的第一输入端，用于接收数字第二本机振荡器（LO）信号和输出的第二输入端。 DDFS（302）被配置为提供作为正交信号的第一和第二LO信号。 相位校正电路（340）被配置为向DDFS（302）的控制输入提供相位校正信号。 第一可选择负载（306）包括耦合到第一混合DAC（336,332）的输出和控制输入的输入。 幅度校正电路（350）被配置为向第一可选择负载（306）的控制输入端提供第一幅度校正信号。

    TECHNIQUES FOR PERFORMING GAIN AND PHASE CORRECTION IN A COMPLEX RADIO FREQUENCY RECEIVER
    7.
    发明申请
    TECHNIQUES FOR PERFORMING GAIN AND PHASE CORRECTION IN A COMPLEX RADIO FREQUENCY RECEIVER 失效
    在复杂无线电频率接收机中执行增益和相位校正的技术

    公开(公告)号：US20080130800A1

    公开(公告)日：2008-06-05

    申请号：US11565499

    申请日：2006-11-30

    申请人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

    发明人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

    IPC分类号： H04L27/08

    CPC分类号： H04L27/3863 ,  H03C3/40

    摘要： A receiver (300) includes a first mixing digital-to-analog converter (DAC) (336, 332), a second mixing DAC (338, 334), a direct digital frequency synthesizer (DDFS) (302), a phase correction circuit (340), a selectable load (306) and a magnitude correction circuit (350). The first mixing DAC (336, 332) includes a first input for receiving an input signal, a second input for receiving a digital first local oscillator (LO) signal and an output. The second mixing DAC (338, 334) includes a first input for receiving the input signal, a second input for receiving a digital second local oscillator (LO) signal and an output The DDFS (302) is configured to provide the first and second LO signals, which are quadrature signals. The phase correction circuit (340) is configured to provide a phase correction signal to a control input of the DDFS (302). The first selectable load (306) includes an input coupled to the output of the first mixing DAC (336, 332) and a control input. The magnitude correction circuit (350) is configured to provide a first magnitude correction signal to the control input of the first selectable load (306).

    摘要翻译： 接收器（300）包括第一混合数模转换器（DAC）（336,332），第二混合DAC（338,334），直接数字频率合成器（DDFS）（302），相位校正电路 （340），可选负载（306）和幅度校正电路（350）。 第一混合DAC（336,332）包括用于接收输入信号的第一输入端，用于接收数字第一本地振荡器（LO）信号和输出的第二输入端。 第二混合DAC（338,334）包括用于接收输入信号的第一输入端，用于接收数字第二本地振荡器（LO）信号和输出端的第二输入端.DDFS（302）被配置为提供第一和第二LO 信号，它们是正交信号。 相位校正电路（340）被配置为向DDFS（302）的控制输入提供相位校正信号。 第一可选择负载（306）包括耦合到第一混合DAC（336,332）的输出和控制输入的输入。 幅度校正电路（350）被配置为向第一可选择负载（306）的控制输入端提供第一幅度校正信号。

    Error correction of data across an isolation barrier
    8.
    发明授权
    Error correction of data across an isolation barrier 失效
    跨越隔离屏障的数据纠错

    公开(公告)号：US07089475B1

    公开(公告)日：2006-08-08

    申请号：US10400182

    申请日：2003-03-26

    申请人： Andrew W. Krone ,  Mitchell Reid

    发明人： Andrew W. Krone ,  Mitchell Reid

    IPC分类号： G06F11/00 ,  H04B1/38

    CPC分类号： H04L25/0298

    摘要： A communication isolation system is provided that may employ error correction techniques for the data communicated across an isolation barrier used for connecting electronic circuitry to a communication line. In one embodiment, each data bit to be transmitted to or from the phone line may be transmitted three times across an isolation barrier so that it is possible to withstand a single electronic fast transient event. In another embodiment, the isolation barrier may be a capacitive isolation barrier. In another embodiment, the three transmissions of the data bit may be received across the isolation barrier and delay elements utilized to provide the data bits to a logic circuit in a synchronized fashion so that the three data bits may be compared to determine the error corrected data.

    摘要翻译： 提供了一种通信隔离系统，其可以对通过用于将电子电路连接到通信线路的隔离屏障传送的数据采用纠错技术。 在一个实施例中，要发送到或来自电话线的每个数据位可以跨隔离屏障传输三次，使得可以承受单个电子快速瞬态事件。 在另一个实施例中，隔离屏障可以是电容隔离屏障。 在另一个实施例中，数据位的三次传输可以跨隔离屏障接收，并且用于以同步的方式将数据位提供给逻辑电路的延迟元件，使得可以比较三个数据位以确定纠错数据 。

    Interface/synchronization circuits for radio frequency receivers with mixing DAC architectures
    10.
    发明授权
    Interface/synchronization circuits for radio frequency receivers with mixing DAC architectures 失效
    具有混合DAC结构的射频接收机的接口/同步电路

    公开(公告)号：US07773968B2

    公开(公告)日：2010-08-10

    申请号：US11565487

    申请日：2006-11-30

    申请人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

    发明人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

    IPC分类号： H04B1/10

    CPC分类号： H04B1/28 ,  H04B1/001 ,  H04B1/0039

    摘要： A receiver (1300) includes a mixing digital-to-analog converter (DAC) (1306), a direct digital frequency synthesizer (DDFS) (132A) and an interface (134D). The mixing DAC (1306) includes a radio frequency (RF) transconductance section (1308) and a switching section (1310). The RE transconductance section (1308) includes an input for receiving an RF signal and an output for providing an RE current signal. The switching section (1310) is coupled to the RF transconductance section (1308) and includes inputs for receiving bits associated with a digital local oscillator (LO) signal and an output that is configured to provide an analog output signal. The DDFS (132A) includes outputs configured to provide the bits associated with the digital LO signal to the inputs of the switching section (1310). The interface (134D) is coupled to the DDFS (132A) and is configured to align the bits provided by the DDFS (132A) with a first clock signal.

    摘要翻译： 接收器（1300）包括混合数模转换器（DAC）（1306），直接数字频率合成器（DDFS）（132A）和接口（134D）。 混合DAC（1306）包括射频（RF）跨导部分（1308）和切换部分（1310）。 RF跨导部分（1308）包括用于接收RF信号的输入端和用于提供RF电流信号的输出端。 开关部分（1310）耦合到RF跨导部分（1308），并且包括用于接收与数字本地振荡器（LO）信号相关联的位的输入和被配置为提供模拟输出信号的输出。 DDFS（132A）包括被配置为将与数字LO信号相关联的位提供给切换部分（1310）的输入的输出。 接口（134D）耦合到DDFS（132A），并且被配置为将由DDFS（132A）提供的位与第一时钟信号对准。