公开(公告)号：US07773968B2

公开(公告)日：2010-08-10

申请号：US11565487

申请日：2006-11-30

申请人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

发明人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

IPC分类号： H04B1/10

CPC分类号： H04B1/28 ,  H04B1/001 ,  H04B1/0039

摘要： A receiver (1300) includes a mixing digital-to-analog converter (DAC) (1306), a direct digital frequency synthesizer (DDFS) (132A) and an interface (134D). The mixing DAC (1306) includes a radio frequency (RF) transconductance section (1308) and a switching section (1310). The RE transconductance section (1308) includes an input for receiving an RF signal and an output for providing an RE current signal. The switching section (1310) is coupled to the RF transconductance section (1308) and includes inputs for receiving bits associated with a digital local oscillator (LO) signal and an output that is configured to provide an analog output signal. The DDFS (132A) includes outputs configured to provide the bits associated with the digital LO signal to the inputs of the switching section (1310). The interface (134D) is coupled to the DDFS (132A) and is configured to align the bits provided by the DDFS (132A) with a first clock signal.

摘要翻译： 接收器（1300）包括混合数模转换器（DAC）（1306），直接数字频率合成器（DDFS）（132A）和接口（134D）。 混合DAC（1306）包括射频（RF）跨导部分（1308）和切换部分（1310）。 RF跨导部分（1308）包括用于接收RF信号的输入端和用于提供RF电流信号的输出端。 开关部分（1310）耦合到RF跨导部分（1308），并且包括用于接收与数字本地振荡器（LO）信号相关联的位的输入和被配置为提供模拟输出信号的输出。 DDFS（132A）包括被配置为将与数字LO信号相关联的位提供给切换部分（1310）的输入的输出。 接口（134D）耦合到DDFS（132A），并且被配置为将由DDFS（132A）提供的位与第一时钟信号对准。

公开(公告)号：US07643600B2

公开(公告)日：2010-01-05

申请号：US11565499

申请日：2006-11-30

申请人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

发明人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

IPC分类号： H04L25/40 ,  H04L7/00 ,  H04L25/00

CPC分类号： H04L27/3863 ,  H03C3/40

摘要： A receiver (300) includes a first mixing digital-to-analog converter (DAC) (336, 332), a second mixing DAC (338, 334), a direct digital frequency synthesizer (DDFS) (302), a phase correction circuit (340), a selectable load (306) and a magnitude correction circuit (350). The first mixing DAC (336, 332) includes a first input for receiving an input signal, a second input for receiving a digital first local oscillator (LO) signal and an output. The second mixing DAC (338, 334) includes a first input for receiving the input signal, a second input for receiving a digital second local oscillator (LO) signal and an output. The DDFS (302) is configured to provide the first and second LO signals, which are quadrature signals. The phase correction circuit (340) is configured to provide a phase correction signal to a control input of the DDFS (302). The first selectable load (306) includes an input coupled to the output of the first mixing DAC (336, 332) and a control input. The magnitude correction circuit (350) is configured to provide a first magnitude correction signal to the control input of the first selectable load (306).

摘要翻译： 接收器（300）包括第一混合数模转换器（DAC）（336,332），第二混合DAC（338,334），直接数字频率合成器（DDFS）（302），相位校正电路 （340），可选负载（306）和幅度校正电路（350）。 第一混合DAC（336,332）包括用于接收输入信号的第一输入端，用于接收数字第一本地振荡器（LO）信号和输出的第二输入端。 第二混合DAC（338,334）包括用于接收输入信号的第一输入端，用于接收数字第二本机振荡器（LO）信号和输出的第二输入端。 DDFS（302）被配置为提供作为正交信号的第一和第二LO信号。 相位校正电路（340）被配置为向DDFS（302）的控制输入提供相位校正信号。 第一可选择负载（306）包括耦合到第一混合DAC（336,332）的输出和控制输入的输入。 幅度校正电路（350）被配置为向第一可选择负载（306）的控制输入端提供第一幅度校正信号。

公开(公告)号：US20080130800A1

公开(公告)日：2008-06-05

申请号：US11565499

申请日：2006-11-30

申请人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

发明人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

IPC分类号： H04L27/08

CPC分类号： H04L27/3863 ,  H03C3/40

摘要： A receiver (300) includes a first mixing digital-to-analog converter (DAC) (336, 332), a second mixing DAC (338, 334), a direct digital frequency synthesizer (DDFS) (302), a phase correction circuit (340), a selectable load (306) and a magnitude correction circuit (350). The first mixing DAC (336, 332) includes a first input for receiving an input signal, a second input for receiving a digital first local oscillator (LO) signal and an output. The second mixing DAC (338, 334) includes a first input for receiving the input signal, a second input for receiving a digital second local oscillator (LO) signal and an output The DDFS (302) is configured to provide the first and second LO signals, which are quadrature signals. The phase correction circuit (340) is configured to provide a phase correction signal to a control input of the DDFS (302). The first selectable load (306) includes an input coupled to the output of the first mixing DAC (336, 332) and a control input. The magnitude correction circuit (350) is configured to provide a first magnitude correction signal to the control input of the first selectable load (306).

摘要翻译： 接收器（300）包括第一混合数模转换器（DAC）（336,332），第二混合DAC（338,334），直接数字频率合成器（DDFS）（302），相位校正电路 （340），可选负载（306）和幅度校正电路（350）。 第一混合DAC（336,332）包括用于接收输入信号的第一输入端，用于接收数字第一本地振荡器（LO）信号和输出的第二输入端。 第二混合DAC（338,334）包括用于接收输入信号的第一输入端，用于接收数字第二本地振荡器（LO）信号和输出端的第二输入端.DDFS（302）被配置为提供第一和第二LO 信号，它们是正交信号。 相位校正电路（340）被配置为向DDFS（302）的控制输入提供相位校正信号。 第一可选择负载（306）包括耦合到第一混合DAC（336,332）的输出和控制输入的输入。 幅度校正电路（350）被配置为向第一可选择负载（306）的控制输入端提供第一幅度校正信号。

公开(公告)号：US20080132195A1

公开(公告)日：2008-06-05

申请号：US11565487

申请日：2006-11-30

申请人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

发明人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

IPC分类号： H04B1/16

CPC分类号： H04B1/28 ,  H04B1/001 ,  H04B1/0039

摘要： A receiver (1300) includes a mixing digital-to-analog converter (DAC) (1306), a direct digital frequency synthesizer (DDFS) (132A) and an interface (134D). The mixing DAC (1306) includes a radio frequency (RF) transconductance section (1308) and a switching section (1310). The RE transconductance section (1308) includes an input for receiving an RF signal and an output for providing an RE current signal The switching section (1310) is coupled to the RF transconductance section (1308) and includes inputs for receiving bits associated with a digital local oscillator (LO) signal and an output that is configured to provide an analog output signal. The DDFS (132A) includes outputs configured to provide the bits associated with the digital LO signal to the inputs of the switching section (1310). The interface (134D) is coupled to the DDFS (132A) and is configured to align the bits provided by the DDFS (132A) with a first clock signal

摘要翻译： 接收器（1300）包括混合数模转换器（DAC）（1306），直接数字频率合成器（DDFS）（132A）和接口（134D）。 混合DAC（1306）包括射频（RF）跨导部分（1308）和切换部分（1310）。 RF跨导部分（1308）包括用于接收RF信号的输入端和用于提供RF电流信号的输出。切换部分（1310）耦合到RF跨导部分（1308），并且包括用于接收与数字 本地振荡器（LO）信号和被配置为提供模拟输出信号的输出。 DDFS（132A）包括被配置为将与数字LO信号相关联的位提供给切换部分（1310）的输入的输出。 接口（134D）耦合到DDFS（132A），并且被配置为将由DDFS（132A）提供的位与第一时钟信号

公开(公告)号：US20070075786A1

公开(公告)日：2007-04-05

申请号：US11473993

申请日：2006-06-23

申请人： Adrian Maxim ,  James Kao

发明人： Adrian Maxim ,  James Kao

IPC分类号： H03L7/00

CPC分类号： H03L7/0896 ,  H03L7/0893 ,  H03L7/18 ,  H03L7/193

摘要： A frequency synthesizer includes analog components and digital components. The frequency synthesizer includes at least one shunt regulator that is coupled to a supply rail to provide power to at least one of the digital components. The frequency synthesizer also includes at least one series regulator that is coupled to the supply rail to provide power to at least one of the analog components.

摘要翻译： 频率合成器包括模拟组件和数字组件。 频率合成器包括至少一个并联稳压器，其耦合到电源轨以向至少一个数字组件提供功率。 频率合成器还包括耦合到电源轨的至少一个串联调节器，以向至少一个模拟组件供电。

公开(公告)号：US07145928B1

公开(公告)日：2006-12-05

申请号：US10642774

申请日：2003-08-18

申请人： Adrian Maxim ,  Jaideep Prakash

发明人： Adrian Maxim ,  Jaideep Prakash

IPC分类号： H01S3/00

CPC分类号： H01S5/042 ,  G02F1/0123 ,  H01S5/0427 ,  H03K25/12

摘要： High frequency laser diode (LD) and electro-absorption modulator (EAM) integrated circuit drivers using a cascaded output switch architecture that increases the output current and voltage edge speed and reduces the peaking and ringing of the output waveform, thus improving the deterministic jitter performance. Also disclosed is a method and apparatus that provides a modulation current dependence of both turn-on and turn-off driving currents that lead to an optimal compromise between the edge speed and output overshoot for a wide range of modulation currents. A PTAT temperature dependence of both voltage swing and current level in the predriver assures a low variation of the overshoot and rise/fall time over a wide temperature range. Using the cascaded output switch architecture provides an easy way of on-chip summation of the modulation and bias currents. Biasing the cascode device with a supply and modulation current dependent base voltage provides an optimum headroom output switch.

摘要翻译： 使用级联输出开关架构的高频激光二极管（LD）和电吸收调制器（EAM）集成电路驱动器，可增加输出电流和电压边沿速度，并减少输出波形的峰值和振铃，从而提高确定性抖动性能 。 还公开了一种提供导通和截止驱动电流的调制电流依赖性的方法和装置，其导致宽范围调制电流的边沿速度和输出过冲之间的最佳折中。 在预驱动器中，电压摆幅和电流电平的PTAT温度依赖性确保了在宽温度范围内的过冲变化和上升/下降时间的低变化。 使用级联输出开关架构提供了调制和偏置电流的片上求和的简单方法。 使用电源和调制电流依赖的基极电压来偏置共源共栅器件可提供最佳的净空输出开关。

公开(公告)号：US20060139105A1

公开(公告)日：2006-06-29

申请号：US11023981

申请日：2004-12-28

申请人： Adrian Maxim ,  James Kao

发明人： Adrian Maxim ,  James Kao

IPC分类号： H03L7/00

CPC分类号： H03L7/093 ,  H03L7/0893 ,  H03L7/0898 ,  H03L7/0995 ,  H03L7/18 ,  H03L2207/04

摘要： Several open-loop calibration techniques for phase-locked-loop circuits (PLL) that provide a process, temperature and divider modulus independence for the loop bandwidth and damping factor are disclosed. Two categories of open-loop techniques are presented. The first method uses only a single measurement of the output frequency from the oscillator and adjusts a single PLL loop element that performs a simultaneous calibration of both the loop bandwidth and damping factor. The output frequency is measured for a given value of the oscillator control signal and the charge-pump current is adjusted such that it cancels the process variation of the oscillator gain. The second method uses two separate and orthogonal calibration steps, both of them based on the measurement of the output frequency from the oscillator when a known excitation is applied to the open loop signal path. In the first step the loop bandwidth is calibrated by adjusting the charge-pump current based on the measurement of the forward path gain when applying a constant phase shift between the two clocks that go to the phase frequency detector, while the integral path is hold to a constant value. During the second step the damping factor is calibrated by adjusting the value of the integral loop filter capacitor based on the measurement of the oscillator output frequency when excited with a voltage proportional with the integral capacitor value, while the proportional control component is zeroed-out.

公开(公告)号：US06690240B2

公开(公告)日：2004-02-10

申请号：US10043558

申请日：2002-01-10

申请人： Adrian Maxim ,  Baker Scott, III ,  Edmund M. Schneider ,  Melvin L. Hagge

发明人： Adrian Maxim ,  Baker Scott, III ,  Edmund M. Schneider ,  Melvin L. Hagge

IPC分类号： H03L700

CPC分类号： H03L7/0893 ,  H03L7/093 ,  H03L7/18

摘要： A loop filter device and method for implementing a loop filter for a phase locked loop (“PLL”) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from a PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for a PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.

摘要翻译： 公开了一种用于实现将信号的频率锁定到参考频率的锁相环（“PLL”）电路的环路滤波器的环路滤波器装置和方法。 环路滤波器包括比例路径电路和积分路径电路。 比例路径电路接收电荷泵输出，并且基于用于锁定PLL电路的信号的频率的更新周期的检测到的相位差来确定并保持在整个更新周期期间被引导到PLL电路或从PLL电路获取的电荷 到参考频率。 积分路径电路耦合到比例路径电路，并且积分路径电路接收另一个电荷泵输出，并且基于当前和先前更新周期的相位差来跟踪PLL电路的总电荷电平。

公开(公告)号：US07750704B2

公开(公告)日：2010-07-06

申请号：US12256800

申请日：2008-10-23

申请人： Adrian Maxim ,  James Kao

发明人： Adrian Maxim ,  James Kao

IPC分类号： H03K12/00

CPC分类号： H03L7/0895

摘要： A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.

摘要翻译： 参考时钟发生器包括用于产生周期信号的振荡器，整形电路和滤波器。 整形电路整形周期信号以产生时钟信号。 滤波器位于振荡器和整形电路之间。

公开(公告)号：US20090039935A1

公开(公告)日：2009-02-12

申请号：US12256800

申请日：2008-10-23

申请人： Adrian Maxim ,  James Kao

发明人： Adrian Maxim ,  James Kao

IPC分类号： H03K12/00

CPC分类号： H03L7/0895

摘要： A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.

摘要翻译： 参考时钟发生器包括用于产生周期信号的振荡器，整形电路和滤波器。 整形电路整形周期信号以产生时钟信号。 滤波器位于振荡器和整形电路之间。