Noise reduction in integrated circuits and circuit assemblies
    1.
    发明授权
    Noise reduction in integrated circuits and circuit assemblies 失效
    集成电路和电路组件中的降噪

    公开(公告)号:US5649160A

    公开(公告)日:1997-07-15

    申请号:US447565

    申请日:1995-05-23

    IPC分类号: H04B15/04 G06F12/00

    CPC分类号: H04B15/04 H04B2215/064

    摘要: The present invention encompasses techniques for reducing digital noise in integrated circuits and circuit assemblies, particularly dense mixed-signal integrated circuits, based upon shaping the noise from the digital circuit and concentrating it in a single, or a small number, of parts of the frequency spectrum. Generally, the presence of noise in the analog circuit is less important at certain frequencies, and therefore the spectral peak or peaks from the digital circuit can be carefully placed to result in little or no interference. As an example, a radio receiver might be designed such that the peaks of the digital noise lie between received channels, outside the band edges of each.

    摘要翻译: 本发明包括基于整形来自数字电路的噪声并将其集中在频率的单个或少数部分中的集成电路和电路组件,特别是致密混合信号集成电路中的数字噪声的技术 光谱。 通常,在某些频率下,模拟电路中噪声的存在不太重要,因此可以小心地将来自数字电路的频谱峰值或峰值导致很少或没有干扰。 作为示例,可以设计无线电接收机,使得数字噪声的峰值位于接收的信道之间,每个的频带边缘之外。

    Alternating current power loss detector
    2.
    发明授权
    Alternating current power loss detector 失效
    交流电流损耗检测器

    公开(公告)号:US4855722A

    公开(公告)日:1989-08-08

    申请号:US892702

    申请日:1986-08-01

    IPC分类号: G01R19/165 H02H3/24

    CPC分类号: H02H3/24

    摘要: The duration of time during which an AC power voltage sinusoidal waveform remains between negative voltage threshold -V1 volts, nominally 5% of negative peak voltage -V2 volts, and positive voltage threshold +V1 volts, nominally 5% of peak positive voltage +V2 volts, is detected. By the change in voltage with time exhibited by a sinusoidal waveform in the region of zero voltage crossing, the expected time duration between voltage thresholds in approximately 5% of one-half period of such sinusoidal waveform. If the actual time between voltage thresholds exceeds (nominally) twice this value, or 10% of one-half period, then a power black-out condition is sensed, and a power fault signal is produced.

    摘要翻译: AC电源电压正弦波形保持在负电压阈值-V1伏特,标称值为负峰值电压-V2伏特的5%和正电压阈值+ V1伏之间的持续时间,标称值为峰值正电压+ V2伏特的5% ,被检测到。 通过在零电压交叉区域中由正弦波形显示的电压随时间的变化,在这种正弦波形的一半周期的大约5%的电压阈值之间的预期持续时间。 如果电压阈值之间的实际时间超过(标称)为该值的两倍或半个周期的10%,则检测掉电状态,并产生电源故障信号。

    Efficiency switching voltage converter system
    5.
    发明授权
    Efficiency switching voltage converter system 失效
    效率切换电压转换器系统

    公开(公告)号:US4661764A

    公开(公告)日:1987-04-28

    申请号:US916070

    申请日:1986-10-06

    IPC分类号: H02M3/156 G05F1/46

    CPC分类号: H02M3/1563

    摘要: Disclosed is an improved efficiency switching voltage converter system wherein the semiconductor switching device employed therein is provided with increased gate drive by selectively applying the most effective driving voltage available in the system.

    摘要翻译: 公开了一种改进的效率切换电压转换器系统,其中采用其中的半导体开关器件通过选择性地施加系统中可用的最有效的驱动电压来提供增加的栅极驱动。