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公开(公告)号：US20120182055A1
公开(公告)日：2012-07-19
申请号：US13005835
申请日：2011-01-13
CPC分类号： H03K3/0372 , G06F17/505 , G06F17/5068
摘要： A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC.
摘要翻译： 用于确定触发器电路类型的方法包括执行IC设计的布局，包括分别布置多个触发器中的每一个的主锁存器和从锁存器以分别接收第一和第二时钟信号。 然后可以实现初始IC设计（例如，在硅衬底上）。 实施后，IC可以在第一和第二模式下操作。 在第一模式中，每个触发器的主锁存器被耦合以接收第一时钟信号。 在第二模式中，第一时钟信号被禁止并且主锁存器保持透明。 每个触发器的从锁存器根据第一和第二模式中的第二时钟信号进行操作。 该方法还包括为每个触发器确定该触发器在IC的后续版本中是作为主从触发器还是作为脉冲触发器。
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公开(公告)号：US08305126B2
公开(公告)日：2012-11-06
申请号：US13005835
申请日：2011-01-13
CPC分类号： H03K3/0372 , G06F17/505 , G06F17/5068
摘要： A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC.
摘要翻译： 用于确定触发器电路类型的方法包括执行IC设计的布局，包括分别布置多个触发器中的每一个的主锁存器和从锁存器以分别接收第一和第二时钟信号。 然后可以实现初始IC设计（例如，在硅衬底上）。 实施后，IC可以在第一和第二模式下操作。 在第一模式中，每个触发器的主锁存器被耦合以接收第一时钟信号。 在第二模式中，第一时钟信号被禁止并且主锁存器保持透明。 每个触发器的从锁存器根据第一和第二模式中的第二时钟信号进行操作。 该方法还包括为每个触发器确定该触发器在IC的后续版本中是作为主从触发器还是作为脉冲触发器。
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3.发明授权Microprocessor performance and power optimization through self calibrated inductive voltage droop monitoring and correction 有权微处理器性能和功率优化通过自校准感应电压下垂监测和校正公开(公告)号：US08648645B2
公开(公告)日：2014-02-11
申请号：US12787135
申请日：2010-05-25
IPC分类号： H03K3/01
CPC分类号： H02M3/157 , H02M2001/0025
摘要： Disclosed is a digital voltage regulator system and method for mitigating voltage droop in an integrated circuit. If an unacceptable voltage droop is detected, the digital voltage regulator may take action to allow the power supply voltage to recover. A digital voltage regulator in accordance with embodiments discussed herein detects voltage droop by comparing a power supply voltage measurement with a threshold voltage. The threshold voltage may be calibrated based on power supply voltage measurements taken while the integrated circuit is operating.
摘要翻译： 公开了用于减轻集成电路中的电压下降的数字电压调节器系统和方法。 如果检测到不可接受的电压下降，则数字电压调节器可采取动作以允许电源电压恢复。 根据本文讨论的实施例的数字电压调节器通过将电源电压测量与阈值电压进行比较来检测电压下降。 阈值电压可以基于集成电路运行时所采用的电源电压测量来校准。
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公开(公告)号：US6072945A
公开(公告)日：2000-06-06
申请号：US883547
申请日：1997-06-26
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , Y10S438/927
摘要： An automated apparatus detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.
摘要翻译： 一种自动化设备在集成电路设计中检测电路违规。 从设计的最低层次开始到目前为止，从布局文件提取的寄生（电阻和电容）分量值向上传播。 然后，在最高层次，采用统计算法来计算所有最高级网络的寄生值。 然后将这些值传回下一级，然后在每个级别，使用先前计算的寄生值和EM限制检查布局。 针对每个布局计算峰值电流，AC平均电流和AC均方根电流，然后与违反的过程EM规则进行比较，其中为每个互连规定了最佳线宽和通孔数。
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公开(公告)号：US06763503B1
公开(公告)日：2004-07-13
申请号：US09989597
申请日：2001-11-20
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method for creating a wire load model using specific interconnect configuration information is provided. Further, a program that creates a wire load model by curve-interconnect fitting parasitic information and interconnect configuration information is provided. Further, a computer system capable of creating an accurate wire load model using parasitic information specific to particular metal layers is provided.
摘要翻译： 提供了使用特定互连配置信息创建有线负载模型的方法。 此外，提供了通过曲线互连拟合寄生信息和互连配置信息来创建线负载模型的程序。 此外，提供了能够使用特定于特定金属层的寄生信息来创建精确的有线负载模型的计算机系统。
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公开(公告)号：US5963729A
公开(公告)日：1999-10-05
申请号：US882986
申请日：1997-06-26
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , Y10S438/927
摘要： An automated method detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.
摘要翻译： 一种自动化方法可以检测集成电路设计中的电路违规。 从设计的最低层次开始到目前为止，从布局文件提取的寄生（电阻和电容）分量值向上传播。 然后，在最高层次，采用统计算法来计算所有最高级网络的寄生值。 然后将这些值传回下一级，然后在每个级别，使用先前计算的寄生值和EM限制检查布局。 针对每个布局计算峰值电流，AC平均电流和AC均方根电流，然后与违反的过程EM规则进行比较，其中为每个互连规定了最佳线宽和通孔数。
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7.发明授权Gate substitution based system and method for integrated circuit power and timing optimization 有权基于门代替的系统和方法，用于集成电路功率和时序优化公开(公告)号：US09317641B2
公开(公告)日：2016-04-19
申请号：US12880275
申请日：2010-09-13
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78 , G06F2217/84
摘要： A processing device can identify gates of an integrated circuit design having a slack value less than a predefined slack threshold. The processing device can further, for each of the identified gates, determine (i) a number of nodes of the integrated circuit design that experience a timing slack improvement if the gate is swapped with an alternative implementation having a reduced delay or (ii) a sum of timing slack improvements experienced by nodes of the integrated circuit design if the gate is swapped with the alternative implementation having a reduced delay. The processing device can still further swap the gate with the alternative implementation having the reduced delay if the determined number or sum is greater than a corresponding predetermined threshold.
摘要翻译： 处理装置可以识别具有小于预定义的松弛阈值的松弛值的集成电路设计的门。 对于每个所识别的门，处理装置还可以进一步确定（i）集成电路设计的节点数量，如果用具有减小的延迟的替代实施方式交换门，则可以经历定时松弛改善，或者（ii） 如果与具有减小的延迟的替代实施方式交换门，集成电路设计的节点经历的定时松弛改进的总和。 如果所确定的数量或或大于相应的预定阈值，则处理装置还可以用具有减小的延迟的替代实施方式进一步交换门。
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公开(公告)号：US20120066658A1
公开(公告)日：2012-03-15
申请号：US12880275
申请日：2010-09-13
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78 , G06F2217/84
摘要： A system for selecting gates for an integrated circuit design may include at least one processing device configured to identify gates of the integrated circuit design having a slack value less than a predefined slack threshold. The at least one processing device may be further configured to, for each of the identified gates, determine (i) a number of nodes of the integrated circuit design that experience a timing slack improvement if the gate is swapped with an alternative implementation having a reduced delay or (ii) a sum of timing slack improvements experienced by nodes of the integrated circuit design if the gate is swapped with the alternative implementation having a reduced delay. The at least one processing device may still be further configured to swap the gate with the alternative implementation having the reduced delay if the determined number or sum is greater than a corresponding predetermined threshold.
摘要翻译： 用于选择用于集成电路设计的门的系统可以包括至少一个处理装置，其被配置为识别具有小于预定义的松弛阈值的松弛值的集成电路设计的门。 所述至少一个处理设备还可以被配置为：对于每个所识别的门，确定（i）如果所述门与具有减少的替代实施方式交换，则所述集成电路设计的节点数量经历了定时松弛改善 延迟或（ii）如果与具有减小的延迟的替代实施方式交换门，则集成电路设计的节点经历的定时松弛改善的总和。 如果所确定的数量或或大于相应的预定阈值，则所述至少一个处理装置可以被进一步配置成与具有减小的延迟的替代实施方式交换所述门。
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9.发明申请公开(公告)号：US20110291630A1
公开(公告)日：2011-12-01
申请号：US12787135
申请日：2010-05-25
IPC分类号： G05F1/10
CPC分类号： H02M3/157 , H02M2001/0025
摘要： Disclosed is a digital voltage regulator system and method for mitigating voltage droop in an integrated circuit. If an unacceptable voltage droop is detected, the digital voltage regulator may take action to allow the power supply voltage to recover. A digital voltage regulator in accordance with embodiments discussed herein detects voltage droop by comparing a power supply voltage measurement with a threshold voltage. The threshold voltage may be calibrated based on power supply voltage measurements taken while the integrated circuit is operating.
摘要翻译： 公开了用于减轻集成电路中的电压下降的数字电压调节器系统和方法。 如果检测到不可接受的电压下降，则数字电压调节器可采取动作以允许电源电压恢复。 根据本文讨论的实施例的数字电压调节器通过将电源电压测量与阈值电压进行比较来检测电压下降。 阈值电压可以基于集成电路运行时所采用的电源电压测量来校准。
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