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公开(公告)号：US20080225987A1
公开(公告)日：2008-09-18
申请号：US12006102
申请日：2007-12-28
IPC分类号： H04L23/00
CPC分类号： H03K19/018521 , H03K3/356165
摘要： An embodiment of the present invention relates to a asynchronous interconnection system comprising a transmitter circuit and a receiver circuit inserted between inserted between respective first and second voltage references and having respective transmitter and receiver nodes coupled in a capacitive manner. The receiver circuit comprises: a recovery stage inserted between the first and second voltage references of the receiver circuit and connected to the receiver node; and a state control stage, in turn inserted between the first and second voltage references of the receiver circuit connected to the recovery stage correspondence with a first feedback node providing a first control signal and having a second feedback node connected in a feedback manner to the recovery stage. The recovery stage comprises a first feedback loop connected to the first feedback node and acting in such a way to recover a received voltage signal and a feedback loop connected to the second feedback node of the state control stage and acting in such a way to deactivate the recovery feedback on the receiver node and guarantee that the receiver node is let in a high impedance state.
摘要翻译： 本发明的实施例涉及一种异步互连系统，其包括插入在相应的第一和第二电压基准之间的发射机电路和接收机电路，并且具有以电容方式耦合的相应的发射机和接收机节点。 接收器电路包括：恢复级，其插入在接收器电路的第一和第二参考电压之间并连接到接收器节点; 并且状态控制级又连接在连接到恢复级的接收器电路的第一和第二参考电压之间，与提供第一控制信号的第一反馈节点相对应，并且具有以反馈方式连接到恢复的第二反馈节点 阶段。 恢复阶段包括连接到第一反馈节点的第一反馈环路，并以这样一种方式起作用以恢复接收到的电压信号和连接到状态控制级的第二反馈节点的反馈回路，并以这样的方式使其停用 对接收机节点进行恢复反馈，并保证接收机节点处于高阻抗状态。
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公开(公告)号：US07808276B2
公开(公告)日：2010-10-05
申请号：US11519444
申请日：2006-09-11
IPC分类号： H03K19/094
CPC分类号： H01L25/0657 , G06F13/4077 , H01L2225/06527 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Embodiments of the invention relate to a chip-to-chip communication system including a transmitter and a receiver connected to receive respective transmitter and receiver clock signals. The transmitter includes precharge and evaluation blocks connected to each other and to a transmitter clock terminal. The receiver includes a precharge block connected to a receiver clock terminal. The precharge blocks precharge an output terminal of the transmitter and an input terminal of the receiver, respectively, to a value corresponding to a first voltage reference during a low phase of the transmitter clock signal.
摘要翻译： 本发明的实施例涉及一种包括发射机和接收机的芯片到芯片通信系统，所述发射机和接收机被连接以接收相应的发射机和接收机时钟信号。 发射机包括彼此连接的预充电和评估块以及发射机时钟终端。 接收机包括连接到接收机时钟端口的预充电块。 预充电块在发送器时钟信号的低相位期间，将发送器的输出端子和接收器的输入端子分别预充电到对应于第一电压基准的值。
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3.发明授权Communication system between a first and a second synchronous device that are uncorrelated in time 有权第一和第二同步设备之间的通信系统在时间上不相关公开(公告)号：US08238502B2
公开(公告)日：2012-08-07
申请号：US12345459
申请日：2008-12-29
IPC分类号： H04L7/00
CPC分类号： H04L7/10 , H04L7/0037
摘要： A communication system includes first and second independently clocked devices, comprising, for each device, a transmitter and a receiver connected to each other in a crossed way in correspondence of an inter-chip communication channel. The communication system further comprises a synchronizer in turn including at least a first and a second synchronization block, having respective input terminals connected to the receivers and respective output terminals connected to the transmitters and comprising at least: a test pattern generator that generates a programmable test pattern signal; a pattern detector to check a matching between stored and received test pattern signals and thus lock corresponding clock phases of the synchronization blocks in case of positive result of this check; and a delay block able to change the clock phases until a synchronized condition of the synchronization blocks is verified, this synchronized condition corresponding to a matching between stored and received test pattern signals.
摘要翻译： 通信系统包括第一和第二独立计时装置，对于每个装置，包括对应于芯片间通信信道以交叉方式相互连接的发射机和接收机。 所述通信系统还包括同步器，其又包括至少第一和第二同步块，其具有连接到接收器的相应输入端子和连接到发射器的相应输出端子，并且至少包括：产生可编程测试的测试模式发生器 模式信号; 模式检测器，用于检查存储和接收的测试模式信号之间的匹配，从而在该检查的肯定结果的情况下锁定同步块的相应时钟相位; 以及能够改变时钟相位直到同步块的同步状态被验证的延迟块，该同步条件对应于存储和接收的测试模式信号之间的匹配。
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4.发明授权Communication system for connecting synchronous devices that are uncorrelated in time 有权用于连接不及时相关的同步设备的通信系统公开(公告)号：US07772888B2
公开(公告)日：2010-08-10
申请号：US12345479
申请日：2008-12-29
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： G06F13/4077 , H04L25/0266 , H04L25/028
摘要： A communication system for the connection between timing non-correlated synchronous devices comprising at least one transmitter and one receiver inserted between a first and a second voltage reference and connected to each other through a transmission channel in correspondence with respective transmitting and receiving terminals Advantageously, the receiver comprises at least one asynchronous input stage suitable for receiving on the receiving terminal a datum and associated with a synchronous output stage suitable for transmitting this datum in a synchronized way with a clock signal on a synchronized receiving terminal. A method transmits a datum from a transmitter to a receiver interconnected by a capacitive channel in a communication system for the connection between independently clocked devices.
摘要翻译： 一种用于在定时非相关同步装置之间的连接的通信系统，包括至少一个发射机和一个接收机之间的连接，插入在第一和第二电压基准之间并且通过与相应的发射和接收终端对应的传输信道彼此连接。有利地， 接收机包括至少一个异步输入级，适于在接收终端上接收与同步接收终端上的时钟信号同步的适于发送该数据的同步输出级的数据。 一种方法通过用于在独立计时的设备之间的连接的通信系统中的电容性通道将来自发射器的数据传送到由接收器互连的接收器。
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公开(公告)号：US07821293B2
公开(公告)日：2010-10-26
申请号：US12006102
申请日：2007-12-28
IPC分类号： H03K19/003
CPC分类号： H03K19/018521 , H03K3/356165
摘要： An embodiment of the present invention relates to a asynchronous interconnection system comprising a transmitter circuit and a receiver circuit inserted between inserted between respective first and second voltage references and having respective transmitter and receiver nodes coupled in a capacitive manner. The receiver circuit comprises: a recovery stage inserted between the first and second voltage references of the receiver circuit and connected to the receiver node; and a state control stage, in turn inserted between the first and second voltage references of the receiver circuit connected to the recovery stage correspondence with a first feedback node providing a first control signal and having a second feedback node connected in a feedback manner to the recovery stage. The recovery stage comprises a first feedback loop connected to the first feedback node and acting in such a way to recover a received voltage signal and a feedback loop connected to the second feedback node of the state control stage and acting in such a way to deactivate the recovery feedback on the receiver node and guarantee that the receiver node is let in a high impedance state.
摘要翻译： 本发明的实施例涉及一种异步互连系统，其包括插入在相应的第一和第二电压基准之间的发射机电路和接收机电路，并且具有以电容方式耦合的相应的发射机和接收机节点。 接收器电路包括：恢复级，其插入在接收器电路的第一和第二参考电压之间并连接到接收器节点; 并且状态控制级又连接在连接到恢复级的接收器电路的第一和第二参考电压之间，与提供第一控制信号的第一反馈节点相对应，并且具有以反馈方式连接到恢复的第二反馈节点 阶段。 恢复阶段包括连接到第一反馈节点的第一反馈环路，并以这样一种方式起作用以恢复接收到的电压信号和连接到状态控制级的第二反馈节点的反馈回路，并以这样的方式使其停用 对接收机节点进行恢复反馈，并保证接收机节点处于高阻抗状态。
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6.发明申请COMMUNICATION SYSTEM FOR CONNECTING SYNCHRONOUS DEVICES THAT ARE UNCORRELATED IN TIME 有权用于连接时间不一致的同步设备的通信系统公开(公告)号：US20090168938A1
公开(公告)日：2009-07-02
申请号：US12345479
申请日：2008-12-29
IPC分类号： H04L7/00
CPC分类号： G06F13/4077 , H04L25/0266 , H04L25/028
摘要： A communication system for the connection between timing non-correlated synchronous devices comprising at least one transmitter and one receiver inserted between a first and a second voltage reference and connected to each other through a transmission channel in correspondence with respective transmitting and receiving terminals Advantageously, the receiver comprises at least one asynchronous input stage suitable for receiving on the receiving terminal a datum and associated with a synchronous output stage suitable for transmitting this datum in a synchronized way with a clock signal on a synchronized receiving terminal. A method transmits a datum from a transmitter to a receiver interconnected by a capacitive channel in a communication system for the connection between independently clocked devices.
摘要翻译： 一种用于在定时非相关同步装置之间的连接的通信系统，包括至少一个发射机和一个接收机之间的连接，插入在第一和第二电压基准之间并且通过与相应的发射和接收终端对应的传输信道彼此连接。有利地， 接收机包括至少一个异步输入级，适于在接收终端上接收与同步接收终端上的时钟信号同步的适于发送该数据的同步输出级的数据。 一种方法通过用于在独立计时的设备之间的连接的通信系统中的电容性通道将来自发射器的数据传送到由接收器互连的接收器。
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7.发明申请COMMUNICATION SYSTEM BETWEEN A FIRST AND A SECOND SYNCHRONOUS DEVICE THAT ARE UNCORRELATED IN TIME 有权第一和第二同步设备之间的通信系统在时间上不统一公开(公告)号：US20090168860A1
公开(公告)日：2009-07-02
申请号：US12345459
申请日：2008-12-29
IPC分类号： H04B3/46
CPC分类号： H04L7/10 , H04L7/0037
摘要： A communication system includes first and second independently clocked devices, comprising, for each device, a transmitter and a receiver connected to each other in a crossed way in correspondence of an inter-chip communication channel. The communication system further comprises a synchronizer in turn including at least a first and a second synchronization block, having respective input terminals connected to the receivers and respective output terminals connected to the transmitters and comprising at least: a test pattern generator that generates a programmable test pattern signal; a pattern detector to check a matching between stored and received test pattern signals and thus lock corresponding clock phases of the synchronization blocks in case of positive result of this check; and a delay block able to change the clock phases until a synchronized condition of the synchronization blocks is verified, this synchronized condition corresponding to a matching between stored and received test pattern signals.
摘要翻译： 通信系统包括第一和第二独立计时装置，对于每个装置，包括对应于芯片间通信信道以交叉方式相互连接的发射机和接收机。 所述通信系统还包括同步器，其又包括至少第一和第二同步块，其具有连接到接收器的相应输入端子和连接到发射器的相应输出端子，并且至少包括：产生可编程测试的测试模式发生器 模式信号; 模式检测器，用于检查存储和接收的测试模式信号之间的匹配，从而在该检查的肯定结果的情况下锁定同步块的相应时钟相位; 以及能够改变时钟相位直到同步块的同步状态被验证的延迟块，该同步条件对应于存储和接收的测试模式信号之间的匹配。
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公开(公告)号：US20070092011A1
公开(公告)日：2007-04-26
申请号：US11519444
申请日：2006-09-11
IPC分类号： H04L25/00
CPC分类号： H01L25/0657 , G06F13/4077 , H01L2225/06527 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Embodiments of the invention relate to a chip-to-chip communication system including a transmitter and a receiver connected to receive respective transmitter and receiver clock signals. The transmitter includes precharge and evaluation blocks connected to each other and to a transmitter clock terminal. The receiver includes a precharge block connected to a receiver clock terminal. The precharge blocks precharge an output terminal of the transmitter and an input terminal of the receiver, respectively, to a value corresponding to a first voltage reference during a low phase of the transmitter clock signal.
摘要翻译： 本发明的实施例涉及一种包括发射机和接收机的芯片到芯片通信系统，所述发射机和接收机被连接以接收相应的发射机和接收机时钟信号。 发射机包括彼此连接的预充电和评估块以及发射机时钟终端。 接收机包括连接到接收机时钟端口的预充电块。 预充电块在发送器时钟信号的低相位期间，将发送器的输出端子和接收器的输入端子分别预充电到对应于第一电压基准的值。
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公开(公告)号：US07456637B2
公开(公告)日：2008-11-25
申请号：US11519425
申请日：2006-09-11
IPC分类号： G01R27/26
CPC分类号： G01R31/2891 , G01R31/312 , H01L25/0657 , H01L2225/06513 , H01L2225/06593 , H01L2225/06596 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An embodiment of the present invention relates to a alignment measurement system for measuring alignment between a plurality of chips of a device, the chips being assembled in a three-dimensional stacking configuration and equipped with at least an integrated capacitive sensor, including a multiple-capacitor structure integrated in the capacitive sensor, at least a sensing circuit connected to the multiple-capacitor structure which issues an output voltage, proportional to a variation of a capacitive value of the multiple-capacitor structure of the integrated capacitive sensor of the device and corresponding to a measured misalignment between the chips of the device.
摘要翻译： 本发明的实施例涉及一种用于测量装置的多个芯片之间的对准的对准测量系统，所述芯片被组装成三维堆叠配置并且至少配备有集成电容传感器，所述集成电容传感器包括多电容器 集成在电容传感器中的结构，至少连接到多电容器结构的感测电路，其发出输出电压，其与装置的集成电容传感器的多电容结构的电容值的变化成比例，并且对应于 测量的器件芯片之间的未对准。
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公开(公告)号：US20070067115A1
公开(公告)日：2007-03-22
申请号：US11519425
申请日：2006-09-11
IPC分类号： G01F23/00
CPC分类号： G01R31/2891 , G01R31/312 , H01L25/0657 , H01L2225/06513 , H01L2225/06593 , H01L2225/06596 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An embodiment of the present invention relates to a alignment measurement system for measuring alignment between a plurality of chips of a device, the chips being assembled in a three-dimensional stacking configuration and equipped with at least an integrated capacitive sensor, comprising a multiple-capacitor structure integrated in said capacitive sensor, at least a sensing circuit connected to said multiple-capacitor structure which issues an output voltage, proportional to a variation of a capacitive value of the multiple-capacitor structure of the integrated capacitive sensor of the device and corresponding to a measured misalignment between the chips of the device.
摘要翻译： 本发明的实施例涉及一种用于测量装置的多个芯片之间的对准的对准测量系统，所述芯片被组装成三维堆叠配置并且装备有至少一个集成电容式传感器，所述集成电容传感器包括多电容器 集成在所述电容传感器中的结构，至少一个连接到所述多电容器结构的感测电路，其发出与设备的集成电容传感器的多电容结构的电容值的变化成比例的输出电压，并且对应于 测量的器件芯片之间的未对准。
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