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    CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration
    1.
    发明授权
    CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration 失效
    CMOS伪NMOS可编程电容时间游标和校准方法

    公开(公告)号：US5214680A

    公开(公告)日：1993-05-25

    申请号：US786447

    申请日：1991-11-01

    Applicant: Alberto Gutierrez, Jr. ,  Christopher Koerner ,  Masaharu Goto ,  James O. Barnes

    Inventor： Alberto Gutierrez, Jr. ,  Christopher Koerner ,  Masaharu Goto ,  James O. Barnes

    IPC: G01R31/319 ,  H03K5/00 ,  H03K5/13 ,  H03M1/66 ,  H03M1/68 ,  H03M1/74

    CPC classification number: H03M1/687 ,  G01R31/31922 ,  H03K5/131 ,  H03K5/133 ,  H03M1/66 ,  H03K2005/00097 ,  H03M1/745 ,  H03M1/747

    Abstract: The present invention is a time vernier providing fine timing control of an input signal having coarse timing edges. The time vernier comprises a receiving means for receiving a value representing a desired time delay to be added to the coarse timing edge input. The desired time delay may have both fine and coarse delay aspects. The time vernier also comprises a first decoding means for decoding the fine delay aspect and generating fine delay control signals, as well as a second decoding means for decoding a coarse delay aspect and generating coarse delay control signals. A delay line is also included in the time vernier which has inputs to receive the input signal having coarse timing edges, the fine and coarse delay control signals, and a control voltage which automatically adjusts with temperature and power supply variations, so as to provide for temperature and power supply compensation. The delay line combines the fine and coarse delay signals to provide an output signal with fine timing edges. Furthermore, the architecture of the present invention enables an automated method of calibration in order to adjust fine and coarse delay elements for fabrication process variations and photolithography variations.

    Abstract translation: 本发明是提供具有粗定时边缘的输入信号的精确定时控制的时间游标。 时间游标包括接收装置，用于接收表示要添加到粗时序边缘输入的期望时间延迟的值。 期望的时间延迟可以具有精细和粗略的延迟方面。 时间游标还包括用于解码精细延迟方面并产生精细延迟控制信号的第一解码装置，以及用于解码粗略延迟方面并产生粗略延迟控制信号的第二解码装置。 延时线还包括在时间游标中，其具有用于接收具有粗定时边缘的输入信号的输入，精细和粗略的延迟控制信号以及根据温度和电源变化自动调整的控制电压，以便提供 温度和电源补偿。 延迟线组合精细和粗略的延迟信号，以提供具有精细时序边缘的输出信号。 此外，本发明的架构能够实现自动校准方法，以便调整用于制造工艺变化和光刻变化的精细和粗略的延迟元件。

    Mobile battery consumption analysis system and method of operating on delta charge samples
    2.
    发明授权
    Mobile battery consumption analysis system and method of operating on delta charge samples 有权
    移动电池消耗分析系统及其操作方法

    公开(公告)号：US09510290B2

    公开(公告)日：2016-11-29

    申请号：US13572473

    申请日：2012-08-10

    Applicant: Alberto Gutierrez, Jr.

    Inventor： Alberto Gutierrez, Jr.

    IPC: H04B1/38 ,  H04W52/02 ,  H04M1/725

    CPC classification number: H04W52/0251 ,  H04M1/72522 ,  H04W52/0261 ,  H04W52/0264 ,  H04W52/0296 ,  Y02D70/00

    Abstract: A method for operation of a battery consumption analysis server communicatively coupled to a plurality of mobile devices over radio channels to receive packages of data recorded at each mobile device containing application use, and battery charging and discharging events. By receiving independent sets of information from the mobile device wherein independent sets comprise at least one of wireless phone activities and battery use, combining this information in such a way that the battery consumption or over consumption of specific applications are identified, the apparatus and method configures a display to identify the correspondingly bad applications to a user.

    Abstract translation: 一种电池消耗分析服务器的操作方法，所述电池消耗分析服务器通过无线电信道通信地耦合到多个移动设备，以接收在包含应用使用的每个移动设备处记录的数据包，以及电池充电和放电事件。 通过从移动设备接收独立的信息集合，其中独立集合包括无线电话活动和电池使用中的至少一个，以识别特定应用的电池消耗或过度消费的方式组合该信息，该装置和方法配置 用于向用户识别相应的不良应用的显示器。

    Digital clock with controllable phase skew
    3.
    发明授权
    Digital clock with controllable phase skew 有权
    具有可控相位偏移的数字时钟

    公开(公告)号：US06316982B1

    公开(公告)日：2001-11-13

    申请号：US09540363

    申请日：2000-03-31

    Applicant: Alberto Gutierrez, Jr.

    Inventor： Alberto Gutierrez, Jr.

    IPC: G06F104

    CPC classification number: G06F1/08

    Abstract: A method and apparatus for generating an output clock signal having a frequency fO derived from a reference clock signal having a frequency fR, such that f 0 = M N ⁢ f R , is satisfied, wherein M and N are integers and M

    Abstract translation: 一种用于产生具有从具有频率fR的参考时钟信号导出的频率f0的输出时钟信号的方法和装置，使得满足其中M和N是整数且M

    Wireless customer experience fault analytics system and method of operation
    5.
    发明授权
    Wireless customer experience fault analytics system and method of operation 有权

    公开(公告)号：US09807229B1

    公开(公告)日：2017-10-31

    申请号：US14511442

    申请日：2014-10-10

    Applicant: Alberto Gutierrez, Jr. ,  Chang-Jia Wang

    Inventor： Alberto Gutierrez, Jr. ,  Chang-Jia Wang

    IPC: H04M3/00 ,  H04M3/08 ,  H04W24/04

    CPC classification number: H04M3/085 ,  H04M2207/18 ,  H04W24/04

    Abstract: A minimum confidence level is applied to recognize a localizable wireless system debility from a debility which is invariant from place to place or which cannot be significantly distinguished from service performance levels of comparable mobile user terminals in the network as a whole. Reports received by the population of users of a service or product family are scored, aggregated, normalized, and averaged overall and for each geographic service area. A report is received from a particular end user and the customer operated wireless instrument and transformed into an individual user experience score over a length of time and breadth of locations. The reports provided by the population of users are transformed into a population experience score that reflects usage in the same time and locations reported from the wireless instrument of the particular end user. Various potential causations are considered and those which exceed a minimum level of confidence are presented.

    M-ary modulation for wireless systems
    6.
    发明授权
    M-ary modulation for wireless systems 有权
    无线系统的M-ary调制

    公开(公告)号：US07305609B2

    公开(公告)日：2007-12-04

    申请号：US10349637

    申请日：2003-01-23

    Applicant: Alberto Gutierrez, Jr.

    Inventor： Alberto Gutierrez, Jr.

    IPC: H03M13/03

    CPC classification number: H04L1/006 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0015 ,  H04L1/0068 ,  H04L1/0071 ,  H04L1/08 ,  H04L5/1453

    Abstract: Disclosed is a method of and apparatus for increasing the capacity of a wireless communication system. This is accomplished by having users that can support a higher than base modulation order be required to do so under predetermined conditions such as electrical distance from a base transceiver station (BTS) antenna to a user, the reception of data in a high speed burst (HSD) and the like. The same digital processor apparatus that may be used to provide a base order modulation scheme may be reprogrammed in a more complex fashion to provide signal processing at the higher modulation rate for any given user channel.

    Abstract translation: 公开了一种用于增加无线通信系统的容量的方法和装置。 这是通过在预定条件下（例如从基站收发器（BTS）天线到用户的电距离），以高速脉冲串的数据接收（即， HSD）等。 可以用于提供基本调制方案的相同的数字处理器装置可以以更复杂的方式重新编程，以便为任何给定的用户信道以更高的调制速率提供信号处理。

    Fine/coarse wired-or tapped delay line
    8.
    发明授权
    Fine/coarse wired-or tapped delay line 失效
    精细/粗糙的有线或抽头延迟线

    公开(公告)号：US5243227A

    公开(公告)日：1993-09-07

    申请号：US786459

    申请日：1991-11-01

    Applicant: Alberto Gutierrez, Jr. ,  Christopher Koerner

    Inventor： Alberto Gutierrez, Jr. ,  Christopher Koerner

    IPC: G01R31/28 ,  G01R31/319 ,  H03K5/00 ,  H03K5/13 ,  H03M1/66 ,  H03M1/68 ,  H03M1/74

    CPC classification number: H03K5/131 ,  G01R31/2841 ,  G01R31/31922 ,  H03K5/133 ,  H03M1/66 ,  H03M1/687 ,  H03K2005/00097 ,  H03M1/745 ,  H03M1/747

    Abstract: The present invention is directed to a delay line for providing fine timing adjustment on subsequent edges of an input signal. The delay line comprises a plurality of delay elements for fine tuning the position in time of the timing edges of the input signal. Each delay element has a data input and data output where the data output is connected to the subsequent delay element's data input, thereby forming a delay line with delay elements connected in series. This implementation facilitates the addition of fine increments of delay to be added to the input signal and thereby enable fine tuning of timing edges. Also, included is a wired-OR multiplexor having data inputs connected to the data outputs of the plurality of the delay elements and a control input to select a particular data output to thereby provide an output signal having delayed timing edges.

    Abstract translation: 本发明涉及一种用于在输入信号的后续边缘上提供精细定时调整的延迟线。 延迟线包括多个延迟元件，用于在输入信号的定时边缘的时间内微调该位置。 每个延迟元件具有数据输入和数据输出，其中数据输出连接到后续延迟元件的数据输入，从而形成具有串联连接的延迟元件的延迟线。 该实施方式有助于增加要添加到输入信号的延迟的精细增量，从而实现定时边缘的微调。 此外，包括有线或有效多路复用器，其具有连接到多个延迟元件的数据输出的数据输入和用于选择特定数据输出的控制输入，从而提供具有延迟定时边缘的输出信号。

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