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公开(公告)号：US20090243657A1
公开(公告)日：2009-10-01
申请号：US12058881
申请日：2008-03-31
IPC分类号： H03K19/096 , H01S4/00 , H03L7/00
CPC分类号： G11C19/00 , G06F9/3869 , Y10T29/49002
摘要： Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal. The clock signal can be delayed by the delay gate such that an output of the pipeline buffer is applied to a next stage of a pipeline buffer at a correct time.
摘要翻译： 为快速不平衡管道架构提供了方法和装置。 公开的流水线缓冲器包括串联连接的多个存储器寄存器，多个存储器寄存器中的每一个，诸如触发器，具有使能输入和时钟输入; 以及控制存储器寄存器，其具有驱动多个存储器寄存器的使能输入的输出，由此控制存储器寄存器的输入上的预定二进制值在下一个时钟周期上移位多个存储器寄存器的值。 多个公开的管道自助餐可以被配置为多级配置。 多个存储寄存器中的至少一个可以包括同步流水线缓冲器的锁存储寄存器。 流水线缓冲器可以可选地包括延迟门以延迟时钟信号和反相器以反转延迟的时钟信号。 时钟信号可以由延迟门延迟，使得流水线缓冲器的输出在正确的时间被施加到流水线缓冲器的下一级。
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公开(公告)号：US07667494B2
公开(公告)日：2010-02-23
申请号：US12058881
申请日：2008-03-31
IPC分类号： G11C19/00 , H03K19/173
CPC分类号： G11C19/00 , G06F9/3869 , Y10T29/49002
摘要： Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal. The clock signal can be delayed by the delay gate such that an output of the pipeline buffer is applied to a next stage of a pipeline buffer at a correct time.
摘要翻译： 为快速不平衡管道架构提供了方法和装置。 公开的流水线缓冲器包括串联连接的多个存储器寄存器，多个存储器寄存器中的每一个，诸如触发器，具有使能输入和时钟输入; 以及控制存储器寄存器，其具有驱动多个存储器寄存器的使能输入的输出，由此控制存储器寄存器的输入上的预定二进制值在下一个时钟周期上移位多个存储器寄存器的值。 多个公开的管道自助餐可以被配置为多级配置。 多个存储寄存器中的至少一个可以包括同步流水线缓冲器的锁存储寄存器。 流水线缓冲器可以可选地包括延迟门以延迟时钟信号和反相器以反转延迟的时钟信号。 时钟信号可以由延迟门延迟，使得流水线缓冲器的输出在正确的时间被施加到流水线缓冲器的下一级。
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公开(公告)号：US20060104145A1
公开(公告)日：2006-05-18
申请号：US10990237
申请日：2004-11-16
IPC分类号： G11C8/00
CPC分类号： G06F17/5045
摘要： A method of tiling a customer memory design to configurable memory blocks within a standardized memory matrix. A customer memory capacity and a customer memory width is determined for the customer memory design, and a standardized memory capacity and a standardized memory width is determined for the configurable memory blocks. The customer memory capacity and the customer memory width are selectively transformed by inverse factors based at least in part on a comparison of the customer memory capacity and the standardized memory capacity. Case independent blocks are formed within the configurable memory blocks, where the case independent blocks include gate structures formed in a standardized array in a substrate in which the customer memory design is to be implemented. Case dependent blocks are formed within the configurable memory blocks, where the case dependent blocks are electrically conductive routing layers that selectively connect the case independent blocks according to the transformation of the customer memory design.
摘要翻译： 将客户存储器设计平铺到标准化存储器矩阵内的可配置存储器块的方法。 为客户存储器设计确定客户存储器容量和客户存储器宽度，并且为可配置存储器块确定标准化存储容量和标准化存储器宽度。 至少部分地基于客户存储器容量与标准化存储器容量的比较，客户存储器容量和客户存储器宽度被反向因素选择性地变换。 在可配置的存储器块内形成与箱体无关的块，其中与壳体无关的块包括形成在衬底中的标准化阵列中的栅极结构，其中将实现客户存储器设计。 在可配置的存储器块内部形成与情况相关的块，其中与盒相关的块是根据客户存储器设计的变换选择性地连接不依赖于盒的块的导电路由层。
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公开(公告)号：US07207026B2
公开(公告)日：2007-04-17
申请号：US10990237
申请日：2004-11-16
CPC分类号： G06F17/5045
摘要： A method of tiling a customer memory design to configurable memory blocks within a standardized memory matrix. A customer memory capacity and a customer memory width is determined for the customer memory design, and a standardized memory capacity and a standardized memory width is determined for the configurable memory blocks. The customer memory capacity and the customer memory width are selectively transformed by inverse factors based at least in part on a comparison of the customer memory capacity and the standardized memory capacity. Case independent blocks are formed within the configurable memory blocks, where the case independent blocks include gate structures formed in a standardized array in a substrate in which the customer memory design is to be implemented. Case dependent blocks are formed within the configurable memory blocks, where the case dependent blocks are electrically conductive routing layers that selectively connect the case independent blocks according to the transformation of the customer memory design.
摘要翻译： 将客户存储器设计平铺到标准化存储器矩阵内的可配置存储器块的方法。 为客户存储器设计确定客户存储器容量和客户存储器宽度，并且为可配置存储器块确定标准化存储容量和标准化存储器宽度。 至少部分地基于客户存储器容量与标准化存储器容量的比较，客户存储器容量和客户存储器宽度被反向因素选择性地变换。 在可配置的存储器块内形成与箱体无关的块，其中与壳体无关的块包括形成在衬底中的标准化阵列中的栅极结构，其中将实现客户存储器设计。 在可配置的存储器块内部形成与情况相关的块，其中与盒相关的块是根据客户存储器设计的变换选择性地连接不依赖于盒的块的导电路由层。
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公开(公告)号：US20110099454A1
公开(公告)日：2011-04-28
申请号：US12985850
申请日：2011-01-06
CPC分类号： H03M13/116 , H03M13/1185
摘要： A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B′x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 … 0 0 0 T … 0 0 … … … … … 0 0 … T 0 I I … I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.
摘要翻译： 通过计算x：= Au来计算二进制源消息u，计算y：= B'x，解析p的等式Dp = y，并且并入u和p以产生编码的二进制消息v，其中A是 一个仅由置换子矩阵构成的矩阵，B'是仅由循环置换子矩阵形成的矩阵，D是形式为D =（T 0 ... 0 0 0 T ... 0 0 ...... ...... 0 0 ... T 0 II ... II）其中T是双对角，循环子矩阵，I是身份子矩阵。
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公开(公告)号：US07739471B2
公开(公告)日：2010-06-15
申请号：US11256830
申请日：2005-10-24
IPC分类号： G06F12/02
CPC分类号： G11C8/12 , G11C2207/104
摘要： A method of configuring a random access memory matrix containing partially configured memories in the matrix. The method includes the steps of independently calculating a memory enable signal and a configuration signal for a partially configured memory in each memory tile of the memory matrix. Memory tiles not supported by a memory compiler are determined. A memory wrapper is provided for each tile not supported by the memory compiler. An address controller is inserted in the memory matrix for each tile in a group of tiles. Output signals from each memory location in a memory group having a common group index are combined into a single output signal. A first stripe of memory tiles containing non-configured memory having a first width is selected. A second strip of memory tiles containing configured memory having a second width is also selected.
摘要翻译： 一种在矩阵中配置包含部分配置的存储器的随机存取存储器矩阵的方法。 该方法包括以下步骤：对存储器矩阵的每个存储器块中的部分配置的存储器独立地计算存储器使能信号和配置信号。 确定内存编译器不支持的内存片。 为存储器编译器不支持的每个片提供内存包装器。 在一组瓦片中的每个瓦片的存储矩阵中插入地址控制器。 来自具有公共组索引的存储器组中的每个存储器位置的输出信号被组合成单个输出信号。 选择包含具有第一宽度的非配置存储器的第一条存储器片。 还选择包含具有第二宽度的配置存储器的第二条存储器片。
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公开(公告)号：US07913149B2
公开(公告)日：2011-03-22
申请号：US11613256
申请日：2006-12-20
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1185
摘要： A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B′x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 … 0 0 0 T … 0 0 … … … … … 0 0 … T 0 I I … I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.
摘要翻译： 通过计算x：= Au来计算二进制源消息u，计算y：= B'x，解析p的等式Dp = y，并且并入u和p以产生编码的二进制消息v，其中A是 一个仅由置换子矩阵构成的矩阵，B'是仅由循环置换子矩阵形成的矩阵，D是形式为D =（T 0 ... 0 0 0 T ... 0 0 ...... ...... 0 0 ... T 0 II ... II）其中T是双对角，循环子矩阵，I是身份子矩阵。
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公开(公告)号：US20080168334A1
公开(公告)日：2008-07-10
申请号：US11613256
申请日：2006-12-20
CPC分类号： H03M13/116 , H03M13/1185
摘要： A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B″x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 ⋯ 0 0 0 T ⋯ 0 0 ⋯ ⋯ ⋯ ⋯ ⋯ 0 0 ⋯ T 0 I I ⋯ I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.
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9.发明申请Process and apparatus for placement of cells in an IC during floorplan creation 有权在建立平面布置图时，将单元格放置在IC中的过程和装置公开(公告)号：US20050091625A1
公开(公告)日：2005-04-28
申请号：US10694208
申请日：2003-10-27
CPC分类号： G06F17/5072
摘要： Objects are placed in a rectangle and their coordinates of the objects and are adjusted to establish a substantially uniform density of objects in the rectangle. The evaluation of coordinates is performed by placing the wires between cells coordinates and adjusting the cell coordinates to connect the cells to the wires. The substantially uniform density is achieved by dividing the rectangle into first and second rectangles having equal free areas and into third and fourth rectangles having equal areas of objects. The coordinates of the objects are adjusted based on boundaries between the first and second rectangles and between the third and fourth rectangles.
摘要翻译： 将对象放置在矩形中，并且对象的坐标进行调整，以在矩形中建立大致均匀的对象密度。 坐标的评估是通过将电线放在单元之间进行坐标并调整单元坐标来连接单元与导线。 通过将矩形分成具有相等空闲区域的第一和第二矩形以及具有相同面积的物体的第三和第四矩形来实现基本上均匀的密度。 基于第一和第二矩形之间以及第三和第四矩形之间的边界来调整对象的坐标。
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公开(公告)号：US20050053182A1
公开(公告)日：2005-03-10
申请号：US10656195
申请日：2003-09-04
CPC分类号： H04L7/02 , H03M9/00 , Y10T436/143333
摘要： A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of the desired output frequency. A plurality of catchers identify valid bits of each respective split signal. A shifter shifts valid bits identified by at least some of the catchers by a predetermined number which establishes a de-serialization level for frequency reduction or phase shifting. An output provide an output data stream at the desired output frequency.
摘要翻译： 频率降低或移相电路具有接收具有输入频率和所需输出频率的表示的输入数据流的输入。 分流器将输入数据流分成多个分离信号，每个信号以期望的输出频率的频率分段。 多个捕获器识别每个相应的分离信号的有效位。 移位器将由至少一些捕获器识别的有效位移位预定数量，其建立用于频率降低或相移的解串级。 输出提供所需输出频率的输出数据流。
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