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    Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation
    1.
    发明授权
    Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation 失效
    针对频率相关串扰模拟的三维互连结构建模的高效方法

    公开(公告)号：US06418401B1

    公开(公告)日：2002-07-09

    申请号：US09248667

    申请日：1999-02-11

    申请人： Allan H. Dansky ,  Alina Deutsch ,  Gerard V. Kopcsay ,  Phillip J. Restle ,  Howard H. Smith

    发明人： Allan H. Dansky ,  Alina Deutsch ,  Gerard V. Kopcsay ,  Phillip J. Restle ,  Howard H. Smith

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036

    摘要： A method for reducing the computation time and improving the productivity in designing high-performance microprocessor chips that have no failures—due to crosstalk noise. The technique allows a very fast calculation of tables of frequency-dependent circuit parameters needed for accurate crosstalk prediction on lossy on-chip interconnections. These tables of parameters are the basis for CAD tools that perform crosstalk checking on >10K critical nets on typical microprocessor chips. A fast table generation allows for rapid incorporation of design or processing changes and transition to more advanced technologies.

    摘要翻译： 一种减少计算时间并提高设计高性能微处理器芯片的生产率的方法，这些微处理器芯片由于串扰噪声而无故障。 该技术允许非常快速地计算在有损片上互连上精确串扰预测所需的频率相关电路参数表。 这些参数表是在典型微处理器芯片上对> 10K关键网进行串扰检查的CAD工具的基础。 快速表生成允许快速结合设计或处理更改并转换到更先进的技术。

    Method to include delta-I noise on chip using lossy transmission line representation for the power mesh
    5.
    发明授权
    Method to include delta-I noise on chip using lossy transmission line representation for the power mesh 失效
    使用功率网格的有损传输线表示在芯片上包括Δ-I噪声的方法

    公开(公告)号：US06963204B2

    公开(公告)日：2005-11-08

    申请号：US10818578

    申请日：2004-04-06

    申请人： Alina Deutsch ,  Gerard V. Kopcsay ,  Byron L. Krauter ,  Barry J. Rubin ,  Howard H. Smith

    发明人： Alina Deutsch ,  Gerard V. Kopcsay ,  Byron L. Krauter ,  Barry J. Rubin ,  Howard H. Smith

    IPC分类号： G01R21/00 ,  G01R29/26 ,  G01R31/317 ,  G05B24/02 ,  G05F1/00 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H02J1/00 ,  H02J3/12 ,  H02J3/18

    CPC分类号： G01R31/31721 ,  H01L23/5225 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： The present invention relates to a method for analyzing the noise prediction within one or more electrical circuits, wherein the electrical circuits have a power mesh grid distribution system that feeds power levels to the electrical circuits that are connected by signal wires. After identifying a driver and receiver electrical circuit to be analyzed, a power block is generated that is associated with the driver and receiver electrical circuit by partitioning an area of a power mesh grid distribution system into a power block that can be modeled with lossy transmission line techniques. Next, signal wires situated between the driver and receiver electrical circuits are partitioned into signal blocks that can be modeled with lossy transmission line techniques. Lastly, the power blocks and signal blocks associated with the electrical circuits are analyzed in order to predict the noise performance within the electrical circuits.

    摘要翻译： 本发明涉及一种用于分析一个或多个电路内的噪声预测的方法，其中电路具有功率网格分布系统，其将功率电平馈送到通过信号线连接的电路。 在识别要分析的驱动器和接收器电路之后，通过将功率网格分布系统的区域划分成可以用有损传输线建模的功率块来产生与驱动器和接收器电路相关联的功率块 技术 接下来，位于驱动器和接收器电路之间的信号线被分割成可以用有损传输线技术建模的信号块。 最后，分析与电路相关联的功率块和信号块，以便预测电路内的噪声性能。

    Method for performing coupling analysis
    6.
    发明授权
    Method for performing coupling analysis 失效
    执行耦合分析的方法

    公开(公告)号：US06546529B1

    公开(公告)日：2003-04-08

    申请号：US09677362

    申请日：2000-10-02

    申请人： Allan H. Dansky ,  Michael A. Bowen ,  Peter J. Camporese ,  Alina Deutsch ,  Howard H. Smith

    发明人： Allan H. Dansky ,  Michael A. Bowen ,  Peter J. Camporese ,  Alina Deutsch ,  Howard H. Smith

    IPC分类号： G06F945

    CPC分类号： G06F17/5036

    摘要： Deterministic evaluation of coupling noise voltage is a function of many physical and electrical parameters such as wiring level, widths, spacing, net topologies, drv impedance and slew rates. This evaluation requires electrical modeling and subsequent circuit simulation to assess the sensitivities of these parameters. These sensitivities can be categorized as coupling guidelines that can be directly linked through extracted physical design data. This invention discloses the development and implementation of a technique for using a coupling guideline table early in the design of an integrated circuit when all the parameters generally required for coupling noise voltage calculations are not available. The steps include: creating a flat wire routing map of the integrated circuit, identifying the coupled wire segments on the integrated circuit, tracking wire interconnection patterns on the integrated circuit, deriving electrical parameters for the coupled wire segments, and generating a coupling guideline table with parameters for a plurality of electrical parameters. The parameters in the coupling guideline table are applied to the derived electrical parameters and a report is generated that lists the derived electrical parameters that fail to comply with the parameters in the coupling guideline table.

    摘要翻译： 耦合噪声电压的确定性评估是许多物理和电气参数的函数，如布线级别，宽度，间距，网络拓扑，drv阻抗和转换速率。 该评估需要电气建模和后续电路仿真来评估这些参数的灵敏度。 这些敏感性可以归类为可以通过提取的物理设计数据直接相关联的耦合准则。 本发明公开了当耦合噪声电压计算通常需要的所有参数不可用时，在集成电路设计早期使用耦合指南表的技术的开发和实现。 步骤包括：创建集成电路的扁平布线图，识别集成电路上的耦合线段，跟踪集成电路上的导线互连图案，导出耦合的线段的电参数，以及生成具有 用于多个电参数的参数。 耦合准则表中的参数应用于导出的电气参数，并生成报告，列出导出的电气参数不符合耦合指南表中的参数。

    Minimal length method for positioning unit pins in a hierarchically designed VLSI chip
    8.
    发明授权
    Minimal length method for positioning unit pins in a hierarchically designed VLSI chip 失效
    用于在分层设计的VLSI芯片中定位单元引脚的最小长度方法

    公开(公告)号：US06415428B1

    公开(公告)日：2002-07-02

    申请号：US09422287

    申请日：1999-10-21

    申请人： Peter J. Camporese ,  Allan H. Dansky ,  Howard H. Smith

    发明人： Peter J. Camporese ,  Allan H. Dansky ,  Howard H. Smith

    IPC分类号： G06F1750

    CPC分类号： G06F17/5072

    摘要： A method for identifying and positioning sub-optimally positioned unit pins in a hierarchically designed VSLI chip without modifying unit placement, comprising: generating a flat data file, generating a first pin log using the flat data file including data for unit pins and for macro pins of a net, generating a second pin log using the flat data file including data for macro pins of the net, determining a minimal net length using the first pin log and determining a minimum net length using the second pin log, calculating the difference between the minimal net length determined using the first ping log and the minimal net length determmed using the second pin log, identifying sub-optimally positioned unit pins by comparing the calculated difference to a threshold, and repositioning the identified sub-optimally positioned unit pins.

    摘要翻译： 一种用于在不改变单元布置的情况下，将次优定位单元引脚识别和定位在分层设计的VSLI芯片中的方法，包括：生成平坦数据文件，使用包括用于单元引脚和宏引脚的数据的平面数据文件生成第一引脚日志 使用包括网的宏引脚的数据的平坦数据文件生成第二引脚对数，使用第一引脚对数确定最小净长度，并使用第二引脚对数确定最小净长度，计算第 使用第一引脚对数确定的最小净长度和使用第二引脚对数确定的最小净长度，通过将计算出的差异与阈值进行比较来重新定位所识别的次优定位单元引脚，从而识别次优定位单元引脚。

    Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chip
    10.
    发明授权
    Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chip 失效
    识别不是最佳定位在分层设计的VLSI芯片中的单元引脚的方法

    公开(公告)号：US06374394B1

    公开(公告)日：2002-04-16

    申请号：US09422290

    申请日：1999-10-21

    申请人： Peter J. Camporese ,  Allan H. Dansky ,  Howard H. Smith

    发明人： Peter J. Camporese ,  Allan H. Dansky ,  Howard H. Smith

    IPC分类号： G06F1750

    CPC分类号： G06F17/5072

    摘要： A method for identifying unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a “flat” file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units. The other pin log is the same, except it does not include the unit pins and the incremental net length associated with the unit pins. A commercially available program, for example, a Minimum Spanning Tree (MST) program or a Steiner Minimal Tree program is run against every net; once against the nets in the pin log list that includes the pins assigned by the designers of the units, and once against the nets in the pin log list that does not include assigned unit pins. The output of interest of the MST (or similar program) run against the net files with and without pin assignments is a text file containing the net names, number of pins per net with and without unit pins and the difference between the net lengths with and without unit pin assignments. If the difference exceeds a threshold value, that net is identified so that the unit pins can be reassigned by the unit designer or designers.

    摘要翻译： 一种用于识别最初在分层VLSI设计中分配的单元销位置的方法，如果被实现，将增加单元引脚作为一部分的网的净长度。 为了识别单元引脚，当单元集成到顶级设计中时，由单元设计人员分配的单元销位置变为不良位置的选择，将创建具有单元的完成的VLSI设计的“平面”文件 位于芯片上，包括由单元设计师分配的针位置。 平面文件不仅包括顶层单元数据和单元到单元净数据，而且还包括每个单元设计的宏数据和宏网数据。 平面设计数据文件用于生成两个引脚日志; 一个针脚日志包括每个网络的增量长度，包括与单元设计者分配的单位引脚（如果有的话）相关联的增量长度。 另一个引脚日志是相同的，除了它不包括单位引脚和与单元引脚相关联的增量净长度。 针对每个网络运行市售程序，例如最小生成树（MST）或Steiner最小树程序; 一次针对引脚日志列表中的网络，其中包括由单元的设计者分配的引脚，并且一次针对不包括分配的单元引脚的引脚日志列表中的网络。 MST（或类似程序）对带有和不带引脚分配的网络文件的兴趣的输出是一个文本文件，其中包含网络名称，每个带有和不带有单元引脚的网络引脚数，以及与/ 没有单位引脚分配。 如果差异超过阈值，则识别该网络，使得单元引脚可由单元设计者或设计者重新分配。