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公开(公告)号:US20230110671A1
公开(公告)日:2023-04-13
申请号:US17495879
申请日:2021-10-07
Applicant: Allegro MicroSystems, LLC
Inventor: Shixi Louis Liu , Paul A. David , Natasha Healey
IPC: G01R19/00 , H01L23/495 , G01R15/20
Abstract: A current sensor integrated circuit configured to sense a current through a current conductor includes a lead frame at least one signal lead, a fan out wafer level package (FOWLP), and a mold material enclosing the FOWLP and a portion of the lead frame. The FOWLP includes a semiconductor die configured to support at least one magnetic field sensing element to sense a magnetic field associated with the current, wherein the semiconductor die has a first surface on which at least one connection pad is accessible, a redistribution layer in contact with the at least one connection pad, and an insulating layer in contact with the redistribution layer, wherein the insulating layer is configured to extend beyond a periphery of the semiconductor die by a minimum distance. The die connection pad is configured to be electrically coupled to the at least one signal lead.
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公开(公告)号:US20230060219A1
公开(公告)日:2023-03-02
申请号:US18053480
申请日:2022-11-08
Applicant: Allegro MicroSystems, LLC
Inventor: Shixi Louis Liu , Robert A. Briano , Natasha Healey
Abstract: A packaged current sensor integrated circuit includes a primary conductor having an input portion and an output portion configured to carry a current to be measured by one or more magnetic sensing elements supported by a semiconductor die adjacent to the primary conductor. A method of fabricating the packaged current sensor integrated circuit includes partially encasing the lead frame in a first mold material, applying an insulator to one or more die attach pads, attaching a die to the insulator, electrically connecting the die to secondary leads, and providing a second mold to the subassembly. The package is configured to provide increased voltage isolation.
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公开(公告)号:US11519946B1
公开(公告)日:2022-12-06
申请号:US17409011
申请日:2021-08-23
Applicant: Allegro MicroSystems, LLC
Inventor: Simon E. Rock , Alexander Latham , Robert A. Briano , Shixi Louis Liu
IPC: G01R19/165 , G01R33/07
Abstract: A packaged current sensor integrated circuit includes a primary conductor having an input portion and an output portion configured to carry a current to be measured by a magnetic sensing element supported by a semiconductor die adjacent to the primary conductor. Each of the input portion and output portion of the primary conductor is exposed from orthogonal sides of the package body. A fault signal may be provided to indicate an overcurrent condition in the integrated current sensor package. The primary current path may be made of a thick lead frame material to reduce the primary current path resistance.
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公开(公告)号:US20210223292A1
公开(公告)日:2021-07-22
申请号:US16884311
申请日:2020-05-27
Applicant: Allegro MicroSystems, LLC
Inventor: Shixi Louis Liu , Paul A. David , Shaun D. Milano , Rishikesh Nikam , Alexander Latham , Wade Bussing , Natasha Healey , Georges El Bacha
Abstract: A current sensor integrated circuit (IC) includes a unitary lead frame having at least one first lead having a terminal end, at least one second lead having a terminal end, and a paddle having a first surface and a second opposing surface. A semiconductor die is supported by the first surface of the paddle, wherein the at least one first lead is electrically coupled to the semiconductor die and the at least one second lead is electrically isolated from the semiconductor die. The current sensor IC further includes a first mold material configured to enclose the semiconductor die and the paddle and a second mold material configured to enclose at least a portion of the first mold material, wherein the terminal end of the at least one first lead and the terminal end of the at least one second lead are external to the second mold material.
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公开(公告)号:US10049969B1
公开(公告)日:2018-08-14
申请号:US15624875
申请日:2017-06-16
Applicant: Allegro MicroSystems, LLC
Inventor: Shixi Louis Liu
IPC: H01L23/495 , H01L23/31 , H01L21/56 , H01L23/00 , H01L25/065
Abstract: An integrated circuit includes a lead frame having a die attach paddle with a slot extending through the die attach paddle from a first surface to a second surface. A plurality of semiconductor die are positioned such that a channel is formed between the first, second, and third semiconductor die and the slot of the die attach paddle. A mold material encloses the plurality of semiconductor die and at least a portion of the lead frame and is disposed in the channel such that the second surface of the die attach paddle is substantially flush with the mold material. A method of forming an integrated circuit is also provided.
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公开(公告)号:US20250164529A1
公开(公告)日:2025-05-22
申请号:US18512122
申请日:2023-11-17
Applicant: Allegro MicroSystems, LLC
Inventor: Maxwell McNally , Alexander Latham , Shixi Louis Liu , William P. Taylor
Abstract: Methods and apparatus for a current sensor integrated circuit package that includes a die having a first magnetic field sensing element and a leadframe to support the die. The leadframe has a U-shaped current conductor loop with a throat region and a first notch in the throat region of the current conductor loop. A first magnetic field sensing element is positioned in relation to the first notch. In some embodiments, the first magnetic field sensing element is aligned with an edge of the first notch.
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公开(公告)号:US20250062198A1
公开(公告)日:2025-02-20
申请号:US18450494
申请日:2023-08-16
Applicant: Allegro MicroSystems, LLC
Inventor: Matthew Hein , Shixi Louis Liu , William P. Taylor
IPC: H01L23/495 , H01L23/00 , H01L23/31 , H01L25/065 , H10N52/80
Abstract: A current sensor IC includes a lead frame having a first surface, a second opposite surface and including a primary conductor and signal leads. A first semiconductor die has a first surface adjacent to the first surface of the lead frame and supporting a first magnetic field sensing element and a second semiconductor die has a first surface adjacent to the second surface of the lead frame and a second opposite surface supporting a second magnetic field sensing element. Fabrication methods include a single mold method and a two-mold method in which a mold material can provide isolation between the first semiconductor die and the primary conductor. Also described is a current sensor IC in which both first and second semiconductor die are arranged in a flip-chip configuration. Diagnostic circuits and inter-die connections permit one semiconductor die to sense faults with the other semiconductor die.
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公开(公告)号:US12183662B2
公开(公告)日:2024-12-31
申请号:US18618259
申请日:2024-03-27
Applicant: Allegro MicroSystems, LLC
Inventor: Robert A. Briano , Shixi Louis Liu , William P. Taylor
IPC: H01L23/495 , H01L23/00
Abstract: Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, an isolator includes a leadframe having first and second die paddles each having opposed first and second surfaces, a first die supported by the first surface of the first die paddle, and a second die supported by the first surface of the second die paddle. The first and second die paddles are configured enhanced creepage characteristics.
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公开(公告)号:US20210082789A1
公开(公告)日:2021-03-18
申请号:US16574621
申请日:2019-09-18
Applicant: Allegro MicroSystems, LLC
Inventor: Robert A. Briano , Shixi Louis Liu , William P. Taylor
IPC: H01L23/495 , H01L23/00
Abstract: Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.
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公开(公告)号:US10753963B2
公开(公告)日:2020-08-25
申请号:US16426215
申请日:2019-05-30
Applicant: Allegro MicroSystems, LLC
Inventor: Shaun D. Milano , Shixi Louis Liu
IPC: G01R15/20 , H01L43/02 , H01L43/04 , H01L43/06 , H01L43/08 , G01R19/00 , G01R33/00 , G01R33/09 , H01L21/48 , G01R33/07 , H01L23/00 , H01L23/495
Abstract: A current sensor integrated circuit includes a lead frame having a primary conductor and at least one secondary lead, a semiconductor die disposed adjacent to the primary conductor, an insulation structure disposed between the primary conductor and the semiconductor die, and a non-conductive insulative material enclosing the semiconductor die, the insulation structure, a first portion of the primary conductor, and a first portion of the at least one secondary lead to form a package. The first portion of the at least one secondary lead (between a first end proximal to the primary conductor and a second end proximal to the second, exposed portion of the at least one secondary lead) has a thickness that is less than a thickness of the second, exposed portion of the least one secondary lead. A distance between the second, exposed portion of the primary conductor and the second, exposed portion of the at least one secondary lead is at least 7.2 mm.
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