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公开(公告)号:US12163983B2
公开(公告)日:2024-12-10
申请号:US18053480
申请日:2022-11-08
Applicant: Allegro MicroSystems, LLC
Inventor: Shixi Louis Liu , Robert A. Briano , Natasha Healey
IPC: G01R15/20 , G01R19/00 , H01L21/66 , H01L23/495
Abstract: A packaged current sensor integrated circuit includes a primary conductor having an input portion and an output portion configured to carry a current to be measured by one or more magnetic sensing elements supported by a semiconductor die adjacent to the primary conductor. A method of fabricating the packaged current sensor integrated circuit includes partially encasing the lead frame in a first mold material, applying an insulator to one or more die attach pads, attaching a die to the insulator, electrically connecting the die to secondary leads, and providing a second mold to the subassembly. The package is configured to provide increased voltage isolation.
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公开(公告)号:US11721648B2
公开(公告)日:2023-08-08
申请号:US17659687
申请日:2022-04-19
Applicant: Allegro MicroSystems, LLC
Inventor: Robert A. Briano , Alejandro Gabriel Milesi
IPC: H01L23/64 , H01L23/552 , H01L23/66 , H03H7/00 , H04L25/02
CPC classification number: H01L23/642 , H01L23/552 , H01L23/66 , H03H7/004 , H04L25/0266
Abstract: Methods and apparatus for a signal isolator having reduced parasitics. An example embodiment, a signal isolator and include a first metal region electrically connected to a first die portion, a second die portion isolated from the first die portion, and a second metal region electrically connected to the second die portion. A third metal region can be electrically isolated from the first and second metal regions and a third die portion can be electrically isolated from the first, second and third metal regions. In embodiments, the first metal region, the second metal region, and the third metal region provide a first isolated signal path from the first die portion to the second die portion.
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公开(公告)号:US20220165647A1
公开(公告)日:2022-05-26
申请号:US17650874
申请日:2022-02-14
Applicant: Allegro MicroSystems, LLC
Inventor: Robert A. Briano , Shixi Louis Liu , William P. Taylor
IPC: H01L23/495 , H01L23/00
Abstract: Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.
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公开(公告)号:US11289406B2
公开(公告)日:2022-03-29
申请号:US16574621
申请日:2019-09-18
Applicant: Allegro MicroSystems, LLC
Inventor: Robert A. Briano , Shixi Louis Liu , William P. Taylor
IPC: H01L23/495 , H01L23/00
Abstract: Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.
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公开(公告)号:US11115244B2
公开(公告)日:2021-09-07
申请号:US16809825
申请日:2020-03-05
Applicant: Allegro MicroSystems, LLC
Inventor: Robert A. Briano , Pedram Sotoodeh Shahnani , Cory Voisine
Abstract: A signal isolator integrated circuit package includes a first circuit having a first input and a first output, a second circuit having a second input and a second output, an isolation barrier layer between the first circuit and the second circuit, wherein the second output of the second circuit is coupled to the first input of the first circuit through the isolation barrier. The signal isolator includes a comparator configured to compare the first input of the first circuit to the second output of the second circuit. The second output can be configured to convey at least three states, including a first state indicative of a logical high of an input signal received at the first input, a second state indicative of a logical low of the input signal, and a third state indicative of a fault condition.
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公开(公告)号:US10753968B2
公开(公告)日:2020-08-25
申请号:US15906291
申请日:2018-02-27
Applicant: Allegro MicroSystems, LLC
Inventor: Robert A. Briano , William P. Taylor
Abstract: Methods and apparatus for an integrated circuit having first and second domains with an insulative material electrically isolating the first and second domains. A conductive shield is disposed between the first and second domains and a current sensor has at least one magnetoresistive element proximate the shield to detect current flow in the shield due to breakdown of the insulative material.
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公开(公告)号:US20240047314A1
公开(公告)日:2024-02-08
申请号:US18490815
申请日:2023-10-20
Applicant: Allegro MicroSystems, LLC
Inventor: Robert A. Briano , Shixi Louis Liu
IPC: H01L23/495 , H01L23/31 , H10N52/00 , G01R15/20 , G01R19/00
CPC classification number: H01L23/49541 , H01L23/3107 , H10N52/00 , G01R15/202 , G01R19/0092 , H01L2224/48245 , H01L24/48
Abstract: A current sensor integrated circuit package includes a primary conductor having an input portion and an output portion, both with reduced area edges. Secondary leads each have an exposed portion and an elongated portion that is offset with respect to the exposed portion. A semiconductor die is disposed adjacent to the primary conductor on an insulator portion and at least one magnetic field sensing element is supported by the semiconductor die. A package body includes a first portion enclosing the semiconductor die and a portion of the primary conductor and a second portion enclosing the elongated portion of the plurality of secondary leads. The first package body portion has a first width configured to expose the input and output portions of the primary conductor and the second package body portion has a second width between a first and second package body side edges that is larger than the first width.
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公开(公告)号:US20240044946A1
公开(公告)日:2024-02-08
申请号:US17817796
申请日:2022-08-05
Applicant: Allegro MicroSystems, LLC
Inventor: Robert A. Briano , Michael C. Doogue , William P. Taylor
CPC classification number: G01R19/0092 , H01L23/4951 , H01L23/49531 , H01L21/4821 , H01L24/45 , G01R15/146 , H05K1/189 , H05K1/181 , H05K1/111 , H05K3/301 , H01L2224/4502 , H05K2201/09227 , H05K2201/09445 , H05K2201/10151 , H05K2201/10636 , H05K2201/10977
Abstract: A sensor package comprising a lead frame, a current sensor die, and an interposer. The lead frame includes: (i) a primary conductor, (ii) a plurality of secondary leads, and (iii) a layer of dielectric material that is disposed between the primary conductor and the plurality of secondary leads. The current sensor die includes one or more sensing elements. The current sensor die is configured to measure a level of electrical current through the primary conductor of the lead frame. The interposer is disposed over the layer of dielectric material. The interposer includes a plurality of conductive traces that are configured to couple each of a plurality of terminals of the current sensor die to a respective one of the plurality of secondary leads.
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公开(公告)号:US11342288B2
公开(公告)日:2022-05-24
申请号:US16430849
申请日:2019-06-04
Applicant: Allegro MicroSystems, LLC
Inventor: Robert A. Briano , Alejandro Gabriel Milesi
IPC: H01L23/64 , H01L23/66 , H01L23/552 , H03H7/00 , H04L25/02
Abstract: Methods and apparatus for a signal isolator having reduced parasitics. An example embodiment, a signal isolator and include a first metal region electrically connected to a first die portion, a second die portion isolated from the first die portion, and a second metal region electrically connected to the second die portion. A third metal region can be electrically isolated from the first and second metal regions and a third die portion can be electrically isolated from the first, second and third metal regions. In embodiments, the first metal region, the second metal region, and the third metal region provide a first isolated signal path from the first die portion to the second die portion.
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公开(公告)号:US11320466B1
公开(公告)日:2022-05-03
申请号:US17083487
申请日:2020-10-29
Applicant: Allegro MicroSystems, LLC
Inventor: Robert A. Briano , Wade Bussing , Timothy A. Clark
Abstract: Methods and apparatus for measuring a current difference between at least two current traces in a circuit board. Each wire or trace generates a magnetic field which may then be measured by at least one magnetic field sensing element positioned on an integrated circuit, such as a current sensor integrated circuit or a differential magnetic field sensor integrated circuit. An output disconnect signal may be provided from the current sensor or differential magnetic field sensing integrated circuit to indicate that a current difference above a predetermined threshold exists in the two or more current traces.
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