公开(公告)号：US08611172B2

公开(公告)日：2013-12-17

申请号：US13476218

申请日：2012-05-21

申请人： Amaranth Shyanmugam ,  Bikas Maiti ,  Vincent Phillipe Schuppe ,  Yew Keong Chong ,  Martin Jay Kinkade ,  Hsin-Yu Chen

发明人： Amaranth Shyanmugam ,  Bikas Maiti ,  Vincent Phillipe Schuppe ,  Yew Keong Chong ,  Martin Jay Kinkade ,  Hsin-Yu Chen

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C8/08 ,  G11C11/418

摘要： A semiconductor memory storage device having a plurality of storage cells for storing data, each storage cell comprising an access control device and access control circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line to: control the voltage control switching circuitry to connect the at least one capacitor to the voltage supply line such that the at least one capacitor is charged by the voltage supply line and a voltage level on the voltage supply line is reduced; and to control the access control line switching circuitry to connect the selected access control line to the voltage supply line having the reduced voltage level.

摘要翻译： 一种具有用于存储数据的多个存储单元的半导体存储器存储装置，每个存储单元包括访问控制装置和访问控制电路。 访问控制电路被配置为响应数据访问请求信号以访问连接到相应的所选访问控制线路的所选择的存储单元，以便：控制电压控制切换电路以将至少一个电容器连接到电压供应线，使得 所述至少一个电容器由所述电压供给线充电，并且所述电压供给线上的电压电平减小; 并且控制访问控制线路切换电路将所选择的访问控制线路连接到具有降低的电压电平的电压供应线路。

公开(公告)号：US20130308407A1

公开(公告)日：2013-11-21

申请号：US13476218

申请日：2012-05-21

申请人： Amaranth Shyanmugam ,  Bikas Maiti ,  Vincent Philippe Schuppe ,  Yew Keong Chong ,  Martin Jay Kinkade ,  Hsin-Yu Chen

发明人： Amaranth Shyanmugam ,  Bikas Maiti ,  Vincent Philippe Schuppe ,  Yew Keong Chong ,  Martin Jay Kinkade ,  Hsin-Yu Chen

IPC分类号： G11C5/14

CPC分类号： G11C7/02 ,  G11C8/08 ,  G11C11/418

摘要： A semiconductor memory storage device having a plurality of storage cells for storing data, each storage cell comprising an access control device and access control circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line to: control the voltage control switching circuitry to connect the at least one capacitor to the voltage supply line such that the at least one capacitor is charged by the voltage supply line and a voltage level on the voltage supply line is reduced; and to control the access control line switching circuitry to connect the selected access control line to the voltage supply line having the reduced voltage level.

摘要翻译： 一种具有用于存储数据的多个存储单元的半导体存储器存储装置，每个存储单元包括访问控制装置和访问控制电路。 访问控制电路被配置为响应数据访问请求信号以访问连接到相应的所选访问控制线路的所选择的存储单元，以便：控制电压控制切换电路以将至少一个电容器连接到电压供应线，使得 所述至少一个电容器由所述电压供给线充电，并且所述电压供给线上的电压电平减小; 并且控制访问控制线路切换电路将所选择的访问控制线路连接到具有降低的电压电平的电压供应线路。

公开(公告)号：US20110158021A1

公开(公告)日：2011-06-30

申请号：US12926965

申请日：2010-12-20

申请人： Jacek Wiatrowski ,  Martin Jay Kinkade ,  Yew Keong Chong

发明人： Jacek Wiatrowski ,  Martin Jay Kinkade ,  Yew Keong Chong

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C11/413 ,  G11C2207/2227

摘要： A semiconductor memory storage device is disclosed. The semiconductor memory storage devices comprises: a plurality of data storage cells arranged in an array. The array comprises a plurality of columns and a plurality of rows, each column comprising at least one output line for outputting a data value from a data storage cell in a selected row of the column. Precharge circuitry for precharging the output lines to a predetermined voltage, the precharge circuitry comprising a plurality of switching devices corresponding to the plurality of columns each switching device controlled by a data output request signal and a power mode signal. The plurality of switching devices each comprising at least two switches, the at least two switches comprising a data output switch controlled by the data output request signal and a power switch controlled by the power mode signal, the plurality of switching devices connecting the output lines to the predetermined voltage in response to both the power mode signal indicating an operational mode and the data output request signal indicating data is to be output; wherein the power mode switch is configured to have a higher capacitance than the data output switch.

摘要翻译： 公开了一种半导体存储器存储装置。 半导体存储器存储装置包括：以数组排列的多个数据存储单元。 阵列包括多个列和多个行，每列包括至少一个输出线，用于从列的选定行中的数据存储单元输出数据值。 用于将输出线预充电到预定电压的预充电电路，所述预充电电路包括对应于多列的多个开关装置，每个开关装置由数据输出请求信号和功率模式信号控制。 所述多个开关装置各自包括至少两个开关，所述至少两个开关包括由所述数据输出请求信号控制的数据输出开关和由所述功率模式信号控制的功率开关，所述多个开关装置将所述输出线连接到 要输出指示操作模式的功率模式信号和指示数据的数据输出请求信号的预定电压; 其中所述功率模式开关被配置为具有比所述数据输出开关更高的电容。

公开(公告)号：US08358551B2

公开(公告)日：2013-01-22

申请号：US12926965

申请日：2010-12-20

申请人： Jacek Wiatrowski ,  Martin Jay Kinkade ,  Yew Keong Chong

发明人： Jacek Wiatrowski ,  Martin Jay Kinkade ,  Yew Keong Chong

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C11/413 ,  G11C2207/2227

摘要： A semiconductor memory storage device is disclosed. The semiconductor memory storage devices comprises: a plurality of data storage cells arranged in an array. The array comprises a plurality of columns and a plurality of rows, each column comprising at least one output line for outputting a data value from a data storage cell in a selected row of the column. Precharge circuitry for precharging the output lines to a predetermined voltage, the precharge circuitry comprising a plurality of switching devices corresponding to the plurality of columns each switching device controlled by a data output request signal and a power mode signal. The plurality of switching devices each comprising at least two switches, the at least two switches comprising a data output switch controlled by the data output request signal and a power switch controlled by the power mode signal, the plurality of switching devices connecting the output lines to the predetermined voltage in response to both the power mode signal indicating an operational mode and the data output request signal indicating data is to be output; wherein the power mode switch is configured to have a higher capacitance than the data output switch.

摘要翻译： 公开了一种半导体存储器存储装置。 半导体存储器存储装置包括：以数组排列的多个数据存储单元。 阵列包括多个列和多个行，每列包括至少一个输出线，用于从列的选定行中的数据存储单元输出数据值。 用于将输出线预充电到预定电压的预充电电路，所述预充电电路包括对应于多列的多个开关装置，每个开关装置由数据输出请求信号和功率模式信号控制。 所述多个开关装置各自包括至少两个开关，所述至少两个开关包括由所述数据输出请求信号控制的数据输出开关和由所述功率模式信号控制的功率开关，所述多个开关装置将所述输出线连接到 要输出指示操作模式的功率模式信号和指示数据的数据输出请求信号的预定电压; 其中所述功率模式开关被配置为具有比所述数据输出开关更高的电容。

公开(公告)号：US08218391B2

公开(公告)日：2012-07-10

申请号：US12801925

申请日：2010-07-01

申请人： Martin Jay Kinkade ,  Gus Yeung ,  Yew Keong Chong

发明人： Martin Jay Kinkade ,  Gus Yeung ,  Yew Keong Chong

IPC分类号： G11C5/14

CPC分类号： G11C5/14

摘要： An integrated circuit memory 10, 12 has clock control circuitry 36 responsive to a clock signal CLK and a chip enable signal CEN to generate control signals for controlling the integrated circuit memory 10 in response to the clock signal CLK when the chip enable signal CEN indicates that the integrated circuit memory 10, 12 is active. When the chip enable signal CEN indicates that the integrated circuit memory 10, 12 is disabled, then power control circuitry 38 serve to switch portions of the integrated circuit memory 10, 12, such as word line driver circuitry 24, sense amplifiers 22 and buffer circuitry 30, into a low power state from an operating state. When the chip enable signal CEN activates the integrated circuit memory 10, 12, the power control circuitry 38 switches these portions 24, 22, 30 which are in the low power state back to the operating state.

摘要翻译： 集成电路存储器10,12具有响应于时钟信号CLK和芯片使能信号CEN的时钟控制电路36，以响应于时钟信号CLK而产生用于控制集成电路存储器10的控制信号，当芯片使能信号CEN指示 集成电路存储器10,12是有效的。 当芯片使能信号CEN指示集成电路存储器10,12被禁用时，功率控制电路38用于切换集成电路存储器10,12的部分，例如字线驱动器电路24，读出放大器22和缓冲电路 30，从运行状态进入低功率状态。 当芯片使能信号CEN激活集成电路存储器10,12时，功率控制电路38将处于低功率状态的这些部分24,22,30切换回操作状态。

公开(公告)号：US20120002499A1

公开(公告)日：2012-01-05

申请号：US12801925

申请日：2010-07-01

申请人： Martin Jay Kinkade ,  Gus Yeung ,  Yew Keong Chong

发明人： Martin Jay Kinkade ,  Gus Yeung ,  Yew Keong Chong

IPC分类号： G11C5/14

CPC分类号： G11C5/14

摘要： An integrated circuit memory 10, 12 has clock control circuitry 36 responsive to a clock signal CLK and a chip enable signal CEN to generate control signals for controlling the integrated circuit memory 10 in response to the clock signal CLK when the chip enable signal CEN indicates that the integrated circuit memory 10, 12 is active. When the chip enable signal CEN indicates that the integrated circuit memory 10, 12 is disabled, then power control circuitry 38 serve to switch portions of the integrated circuit memory 10, 12, such as word line driver circuitry 24, sense amplifiers 22 and buffer circuitry 30, into a low power state from an operating state. When the chip enable signal CEN activates the integrated circuit memory 10, 12, the power control circuitry 38 switches these portions 24, 22, 30 which are in the low power state back to the operating state.

公开(公告)号：US07180348B2

公开(公告)日：2007-02-20

申请号：US11088268

申请日：2005-03-24

申请人： Marlin Frederick ,  Martin Jay Kinkade

发明人： Marlin Frederick ,  Martin Jay Kinkade

IPC分类号： H03K3/12

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3296 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/0375 ,  Y02D10/128 ,  Y02D10/172 ,  Y02D50/20

摘要： The application relates to a circuit for storing a signal during sleep mode, said embodiments of the circuit comprising: a sleep signal input operable to receive a sleep signal; a clock signal input operable to receive a clock signal; a plurality of latches clocked by said clock signal, at least one tristateable device clocked by said clock signal, said at least one tristateable device being arranged at an input of at least one of said plurality of latches, said at least one tristateable device being operable to selectively isolate said input of said at least one latch in response to a predetermined clock signal value; clock signal distribution means operable to distribute said clock signal to said plurality of latches and said at least one tristateable device; wherein in response to a sleep signal said circuit is operable to: reduce a voltage difference across at least a portion of said circuit such that said portion of said circuit is powered down; and maintain a voltage difference across at least one storage latch, said at least one storage latch being said at least one of said plurality of latches; said clock signal distribution means being operable to hold said clock signal at said predetermined value such that said input of said storage latch is isolated.

摘要翻译： 本申请涉及一种用于在休眠模式期间存储信号的电路，所述电路的所述实施例包括：可操作以接收睡眠信号的睡眠信号输入; 时钟信号输入，用于接收时钟信号; 由所述时钟信号时钟的多个锁存器，由所述时钟信号时钟的至少一个三态装置，所述至少一个三态装置被布置在所述多个锁存器中的至少一个锁存器的输入端处，所述至少一个三态装置可操作 响应于预定的时钟信号值选择性地隔离所述至少一个锁存器的所述输入; 时钟信号分配装置，用于将所述时钟信号分配给所述多个锁存器和所述至少一个可三态装置; 其中响应于睡眠信号，所述电路可操作以：减少所述电路的至少一部分上的电压差，使得所述电路的所述部分断电; 并且跨越至少一个存储锁存器保持电压差，所述至少一个存储锁存器是所述多个锁存器中的至少一个; 所述时钟信号分配装置可操作以将所述时钟信号保持在所述预定值，使得所述存储锁存器的所述输入被隔离。

公开(公告)号：US07221205B2

公开(公告)日：2007-05-22

申请号：US10883965

申请日：2004-07-06

申请人： Martin Jay Kinkade ,  Marlin Frederick

发明人： Martin Jay Kinkade ,  Marlin Frederick

IPC分类号： H03K3/289

CPC分类号： H03K3/0375

摘要： A clocked scan flip-flop 2 is provided in which a latch 14 within the diagnostic data path is reused to store an operational signal value during a sleep mode. The operational signal value is supplied to the latch 14 via a sleep mode path 20 through a transmission gate 22 (or other tristate driver) controlled by a sleep mode control signal SLP. The diagnostic clock signal SCLK, the operational clock signal CLK and the sleep mode control signal SLP together provide the control operations for controlling the various elements within the clocked-scan flip-flop 2 to move into and out of sleep mode.

摘要翻译： 提供了时钟扫描触发器2，其中诊断数据路径内的锁存器14在睡眠模式期间被重新用于存储操作信号值。 操作信号值经由休眠模式路径20通过由休眠模式控制信号SLP控制的传输门22（或其他三态驱动器）提供给锁存器14。 诊断时钟信号SCLK，操作时钟信号CLK和睡眠模式控制信号SLP一起提供用于控制时钟扫描触发器2内的各种元件进入和退出睡眠模式的控制操作。

公开(公告)号：US07650524B2

公开(公告)日：2010-01-19

申请号：US11386102

申请日：2006-03-22

申请人： Marlin Frederick, Jr. ,  Martin Jay Kinkade

发明人： Marlin Frederick, Jr. ,  Martin Jay Kinkade

IPC分类号： G06F1/04

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3296 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/0375 ,  Y02D10/128 ,  Y02D10/172 ,  Y02D50/20

摘要： The application relates to a circuit for storing a signal during sleep mode, said embodiments of the circuit comprising: a sleep signal input operable to receive a sleep signal; a clock signal input operable to receive a clock signal; a plurality of latches clocked by said clock signal, at least one tristateable device clocked by said clock signal, said at least one tristateable device being arranged at an input of at least one of said plurality of latches, said at least one tristateable device being operable to selectively isolate said input of said at least one latch in response to a predetermined clock signal value; clock signal distribution means operable to distribute said clock signal to said plurality of latches and said at least one tristateable device; wherein in response to a sleep signal said circuit is operable to: reduce a voltage difference across at least a portion of said circuit such that said portion of said circuit is powered down; and maintain a voltage difference across at least one storage latch, said at least one storage latch being said at least one of said plurality of latches; said clock signal distribution means being operable to hold said clock signal at said predetermined value such that said input of said storage latch is isolated.

摘要翻译： 本申请涉及一种用于在休眠模式期间存储信号的电路，所述电路的所述实施例包括：可操作以接收睡眠信号的睡眠信号输入; 时钟信号输入，用于接收时钟信号; 由所述时钟信号时钟的多个锁存器，由所述时钟信号时钟的至少一个三态装置，所述至少一个三态装置被布置在所述多个锁存器中的至少一个锁存器的输入端处，所述至少一个三态装置可操作 响应于预定的时钟信号值选择性地隔离所述至少一个锁存器的所述输入; 时钟信号分配装置，用于将所述时钟信号分配给所述多个锁存器和所述至少一个可三态装置; 其中响应于睡眠信号，所述电路可操作以：减少所述电路的至少一部分上的电压差，使得所述电路的所述部分断电; 并且跨越至少一个存储锁存器保持电压差，所述至少一个存储锁存器是所述多个锁存器中的至少一个; 所述时钟信号分配装置可操作以将所述时钟信号保持在所述预定值，使得所述存储锁存器的所述输入被隔离。

公开(公告)号：US07606108B2

公开(公告)日：2009-10-20

申请号：US11984442

申请日：2007-11-16

申请人： David Anthony New ,  Gus Yeung ,  Martin Jay Kinkade ,  David John Willingham

发明人： David Anthony New ,  Gus Yeung ,  Martin Jay Kinkade ,  David John Willingham

IPC分类号： G11C8/00

CPC分类号： G11C8/16

摘要： A multiport memory 2 is provided with control circuitry 14 which detects signal values indicative of concurrent write and read accesses via respective bit lines of a plurality of data access ports to a common row of bit cells. When such signals are detected, an override signal is generated and supplied to override circuitry 34, 36, 38, 40, 42, 44. The override circuitry is responsive to the override signal to drive one or more bit values being written to respective bit cells via their associated bit lines onto associated bit lines of other of a plurality of data access supports that are concurrently enabled for access to their bit cells. Thus, write data is also written onto the bit lines associated with a port performing a concurrent read operation.

摘要翻译： 多端口存储器2设置有控制电路14，控制电路14通过多个数据访问端口的相应位线检测指示同时写入和读取访问的信号值到公共行位单元。 当检测到这样的信号时，产生超控信号并提供给超控电路34,36,38,40,42,44。超控电路响应超驰信号以驱动被写入相应位单元的一个或多个位值 通过其相关联的位线到多个数据访问支持中的其他数据访问支持的相关联的位线，这些数据访问支持同时被允许访问它们的位单元。 因此，写入数据也被写入与执行并行读取操作的端口相关联的位线上。