公开(公告)号：US12236260B1

公开(公告)日：2025-02-25

申请号：US17643572

申请日：2021-12-09

Applicant: Amazon Technologies, Inc.

Inventor： Dan Saad ,  Guy Nakibly ,  Lev Vaskevich ,  Aviv Bonomo

IPC: G06F9/46 ,  G06F9/54

Abstract: An address decoder for a system is disclosed that can be used for different source nodes in the system. Each address decoder can be configured to perform a plurality of decode methods that can be customized for each source node. A first decode method can be used to determine a target node from a plurality of target nodes based on a destination address of the transaction. A second decode method can be used to assign a dedicated target node as the target node irrespective of the destination address of the transaction. The second decode method can be used to route the transaction to the dedicated target node for testing and verification operations.

公开(公告)号：US11960392B1

公开(公告)日：2024-04-16

申请号：US17643127

申请日：2021-12-07

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Dan Saad ,  Yaniv Shapira ,  Erez Izenberg

IPC: G06F13/14 ,  G06F9/46 ,  G06F12/02 ,  G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G11C11/408

CPC classification number: G06F12/0238 ,  G06F9/467 ,  G06F12/0292 ,  G06F13/1621 ,  G06F13/38 ,  G06F13/4221 ,  G11C11/4087

Abstract: A first configurable address decoder can be coupled between a source node and a first interconnect fabric, and a second address decoder can be coupled between the first interconnect fabric and a second interconnect fabric. The first address decoder can be configured with a first address mapping table that can map a first set of address ranges to a first set of target nodes connected to the first interconnect fabric. The second address decoder can be configured with a second address mapping table that can map a second set of address ranges to a second set of target nodes connected to the second interconnect fabric. The second address decoder can be part of the first set of target nodes. The first address decoder and the second address decoder can be configured or re-configured to determine different routes for a transaction from the source node to a target node in the second set of target nodes via the first and second interconnect fabrics.

公开(公告)号：US11640366B1

公开(公告)日：2023-05-02

申请号：US17457812

申请日：2021-12-06

Applicant: Amazon Technologies, Inc.

Inventor： Dan Saad ,  Guy Nakibly ,  Yaniv Shapira ,  Aviv Bonomo ,  Moshe Gutman

IPC: G06F13/362 ,  G06F13/42 ,  G06F13/40 ,  G06F15/78 ,  G06F9/46

Abstract: An address decoder for a source node in a multi-chip system is disclosed, which can perform parallel decoding steps to determine whether a transaction from the source node is addressed to a target node in a local integrated circuit (IC) or a remote IC, and whether the source node is allowed to access that target node. Based on the outcome of both the decoding steps, the transaction can be either blocked by the address decoder, or routed to the target node. If the transaction is addressed to the remote IC, but the source node is not allowed to access the target node on the remote IC, the transaction can be terminated by the address decoder in the local IC.