公开(公告)号：US08347244B2

公开(公告)日：2013-01-01

申请号：US11927720

申请日：2007-12-11

申请人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Sherman Anatoly ,  Michael Zelikson

发明人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Sherman Anatoly ,  Michael Zelikson

IPC分类号： G06F17/50

CPC分类号： G06F17/5063 ,  G06F2217/86

摘要： A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines.

摘要翻译： 用于模拟和混合信号电路的工具包括使得用户能够识别芯片架构中的一个或多个关键互连线和用于所述关键互连线的一个或多个可选择的预定义拓扑的单元。 每个拓扑包括一个或多个信号线和电流返回路径。 大部分电场线包含在拓扑的边界内。 本发明还包括一种用于设计模拟和混合信号（AMS）集成电路（IC）的方法，包括定义芯片架构和平面图，识别一个或多个关键互连线，并为关键互连选择预先设计的传输线拓扑 线条。

公开(公告)号：US20090150848A1

公开(公告)日：2009-06-11

申请号：US11927720

申请日：2007-12-11

申请人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Anatoly Sherman ,  Michael Zelikson

发明人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Anatoly Sherman ,  Michael Zelikson

IPC分类号： G06F17/50

CPC分类号： G06F17/5063 ,  G06F2217/86

摘要： A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines.

摘要翻译： 用于模拟和混合信号电路的工具包括使得用户能够识别芯片架构中的一个或多个关键互连线和用于所述关键互连线的一个或多个可选择的预定义拓扑的单元。 每个拓扑包括一个或多个信号线和电流返回路径。 大部分电场线包含在拓扑的边界内。 本发明还包括一种用于设计模拟和混合信号（AMS）集成电路（IC）的方法，包括定义芯片架构和平面图，识别一个或多个关键互连线并且为关键互连选择预先设计的传输线拓扑 线条。

公开(公告)号：US07454733B2

公开(公告)日：2008-11-18

申请号：US10091934

申请日：2002-03-06

申请人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Anatoly Sherman ,  Michael Zelikson

发明人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Anatoly Sherman ,  Michael Zelikson

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036 ,  G06F17/5045

摘要： An integrated circuit design kit including one or more circuit components topologies, and one or more critical interconnect lines topologies. The interconnect line topologies may be predefined. The kit may further include one or more circuit components models and one or more critical interconnect lines models.

摘要翻译： 集成电路设计套件包括一个或多个电路组件拓扑，以及一个或多个关键互连线拓扑。 可以预定义互连线拓扑。 该套件还可以包括一个或多个电路组件模型和一个或多个关键互连线模型。

公开(公告)号：US07080340B2

公开(公告)日：2006-07-18

申请号：US10723752

申请日：2003-11-26

申请人： David Goren ,  Rachel Gordin ,  Michael Zelikson

发明人： David Goren ,  Rachel Gordin ,  Michael Zelikson

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： In a system 10 for designing an integrated circuit, a preliminary design of the integrated circuit is defined and critical interconnect lines in the preliminary design are identified. Further, any critical interconnect lines which are affected by crossing lines in the preliminary design are identified, and a transmission line model 35 is defined to represent each critical interconnect line. A layout design of the integrated circuit, comprising circuit components and parameters thereof, is then defined using the preliminary design and the transmission line model 35 for each critical interconnect line. Component parameters are then extracted from the layout design for simulation of the design using the extracted component parameters. During this design process, for each transmission line model 35 representing a critical interconnect line affected by a crossing line, an environment terminal 36 is provided. The environment terminal 36 comprises a connection to the model 35 via at least one circuit component representing the effect of the crossing line on the model. The environment terminal 36 is connected to the appropriate crossing line in the integrated circuit design, whereby crossing line effects are accommodated in the design process.

摘要翻译： 在用于设计集成电路的系统10中，定义了集成电路的初步设计，并且识别了初步设计中的关键互连线。 此外，识别在初步设计中受交叉线影响的任何关键互连线，并且传输线模型35被定义为表示每个关键互连线。 然后使用用于每个关键互连线的初步设计和传输线模型35来定义包括电路部件及其参数的集成电路的布局设计。 然后从布局设计中提取组件参数，以使用提取的组件参数进行设计的仿真。 在该设计过程中，对于表示受交叉线影响的关键互连线的每个传输线模型35，提供环境终端36。 环境终端36包括通过表示模型上的交叉线的影响的至少一个电路组件到模型35的连接。 环境端子36在集成电路设计中连接到适当的交叉线，由此在设计过程中容纳交叉线效应。

公开(公告)号：US20050114819A1

公开(公告)日：2005-05-26

申请号：US10723752

申请日：2003-11-26

申请人： David Goren ,  Rachel Gordin ,  Michael Zelikson

发明人： David Goren ,  Rachel Gordin ,  Michael Zelikson

IPC分类号： G06F17/50 ,  G06F9/455 ,  H01L21/82

CPC分类号： G06F17/5036

摘要： In a system 10 for designing an integrated circuit, a preliminary design of the integrated circuit is defined and critical interconnect lines in the preliminary design are identified. Further, any critical interconnect lines which are affected by crossing lines in the preliminary design are identified, and a transmission line model 35 is defined to represent each critical interconnect line. A layout design of the integrated circuit, comprising circuit components and parameters thereof, is then defined using the preliminary design and the transmission line model 35 for each critical interconnect line. Component parameters are then extracted from the layout design for simulation of the design using the extracted component parameters. During this design process, for each transmission line model 35 representing a critical interconnect line affected by a crossing line, an environment terminal 36 is provided. The environment terminal 36 comprises a connection to the model 35 via at least one circuit component representing the effect of the crossing line on the model. The environment terminal 36 is connected to the appropriate crossing line in the integrated circuit design, whereby crossing line effects are accommodated in the design process.

摘要翻译： 在用于设计集成电路的系统10中，定义了集成电路的初步设计，并且识别了初步设计中的关键互连线。 此外，识别在初步设计中受交叉线影响的任何关键互连线，并且传输线模型35被定义为表示每个关键互连线。 然后使用用于每个关键互连线的初步设计和传输线模型35来定义包括电路部件及其参数的集成电路的布局设计。 然后从布局设计中提取组件参数，以使用提取的组件参数进行设计的仿真。 在该设计过程中，对于表示受交叉线影响的关键互连线的每个传输线模型35，提供环境终端36。 环境终端36包括通过表示模型上的交叉线的影响的至少一个电路组件到模型35的连接。 环境端子36在集成电路设计中连接到适当的交叉线，由此在设计过程中容纳交叉线效应。

公开(公告)号：US08041546B2

公开(公告)日：2011-10-18

申请号：US12137257

申请日：2008-06-11

申请人： Rachel Gordin ,  David Goren

发明人： Rachel Gordin ,  David Goren

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (ε1) and the substrate is a second dielectric with a second permittivity (ε2). The method models the capacitance (C1) for values of the first and second permittivity (ε1, ε2) based on known capacitance (C2) computed for a basis structure with the same first permittivity (ε1) and a different second permittivity (ε2). Extrapolation or interpolation formulae are suggested to model the sought capacitance (C1) through one or more known capacitances (C2).

摘要翻译： 一种用于结构建模的方法，该结构包括由电介质材料包围并由衬底支撑的一对长导体。 特别地，该结构可以是在以非常高的频率操作的导电衬底上的片上共面传输线，使得衬底表现为完美的电介质。 假设周围的电介质材料是具有第一介电常数（第一介电常数）的第一电介质，并且衬底是具有第二介电常数的第二电介质（＆amp; 2）。 该方法基于针对具有相同的第一介电常数（＆egr.1）的基础结构计算的已知电容（C2）和不同的第一介电常数（＆egr.1）的基础结构计算第一和第二介电常数（＆egr; 1，＆egr; 2） 第二介电常数（＆egr。2）。 建议外插或内插公式通过一个或多个已知电容（C2）建模寻找电容（C1）。

公开(公告)号：US07392490B2

公开(公告)日：2008-06-24

申请号：US11123806

申请日：2005-05-06

申请人： Rachel Gordin ,  David Goren

发明人： Rachel Gordin ,  David Goren

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Methods, systems and apparatus for modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (e1) and the substrate is a second dielectric with a second permittivity (e2). A method models the capacitance (C1) for values of the first and second permittivity (e1, e2) based on known capacitance (C2) computed for a basis structure with the same first permittivity (e1) and a different second permittivity (e2). Extrapolation or interpolation formulae are suggested to model the sought capacitance (C1) through one or more known capacitances (C2).

摘要翻译： 用于建模电容的方法，系统和装置，包括由电介质材料围绕并由衬底支撑的一对长导体。 特别地，该结构可以是在以非常高的频率操作的导电衬底上的片上共面传输线，使得衬底表现为完美的电介质。 假设周围的电介质材料是具有第一介电常数（ε1）的第一电介质，并且衬底是具有第二介电常数（e 2 N 2）的第二电介质。 一种方法根据已知的电容对第一和第二介电常数（e 1 1，e 2 2）的值进行建模（C 1> 1 ） 对于具有相同的第一介电常数（e <1> 1）和不同的第二介电常数（e 2> 2）的基础结构计算得到。 建议外推或内插公式，以通过一个或多个已知电容（C 2> 2）来建模所寻找的电容（C 1> 1）。

公开(公告)号：US08271913B2

公开(公告)日：2012-09-18

申请号：US12564061

申请日：2009-09-22

申请人： Roi Carmon ,  David Goren ,  Rachel Gordin ,  Shlomo Shlafman

发明人： Roi Carmon ,  David Goren ,  Rachel Gordin ,  Shlomo Shlafman

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  H01P3/003 ,  H01P3/006

摘要： A method and system for design and modeling of transmission lines are provided. The method includes providing a set of models of core structures (211) of transmission line cells and expanding each of the models of core structures (211) to include different neighboring elements. The parameter characteristics of the expanded core structures (214a-214c) are compared to determine a model having a minimal sufficiently closed neighborhood environment. A closed neighborhood environment complies with design rules to ensure desired transmission line behavior in a real design environment. A model having a closed neighborhood environment can be used as a stand-alone model of the core structure describing the transmission line behavior in the actual design environment.

摘要翻译： 提供了传输线设计和建模的方法和系统。 该方法包括提供传输线路单元的核心结构（211）的一组模型，并且扩展核心结构（211）的每个模型以包括不同的相邻元件。 将扩展的核心结构（214a-214c）的参数特性进行比较，以确定具有最小充分闭合的邻近环境的模型。 封闭的邻里环境符合设计规则，以确保实际设计环境中所需的传输线路行为。 具有封闭邻域环境的模型可以用作描述实际设计环境中的传输线行为的核心结构的独立模型。

公开(公告)号：US20080243453A1

公开(公告)日：2008-10-02

申请号：US12137257

申请日：2008-06-11

申请人： Rachel Gordin ,  David Goren

发明人： Rachel Gordin ,  David Goren

IPC分类号： G06G7/48

CPC分类号： G06F17/5036

摘要： A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (ε1) and the substrate is a second dielectric with a second permittivity (ε2). The method models the capacitance (C1) for values of the first and second permittivity (ε1, ε2) based on known capacitance (C2) computed for a basis structure with the same first permittivity (ε1) and a different second permittivity (ε2). Extrapolation or interpolation formulae are suggested to model the sought capacitance (C1) through one or more known capacitances (C2).

摘要翻译： 一种用于结构建模的方法，该结构包括由电介质材料包围并由衬底支撑的一对长导体。 特别地，该结构可以是在以非常高的频率操作的导电衬底上的片上共面传输线，使得衬底表现为完美的电介质。 假设周围的电介质材料是具有第一介电常数（ε1> 1）的第一电介质，并且衬底是具有第二介电常数（ε2/2）的第二电介质。 该方法基于已知的电容（第一和第二介电常数（ε1，ε2，ε2））对第一和第二介电常数（ε1，ε2，ε2 2）的值建模电容（C 1 SUB） 对于具有相同的第一介电常数（ε1> 1）和不同的第二介电常数（ε2> 2）的基础结构计算出的C 2 C 2 N 2）。 建议外推或内插公式，以通过一个或多个已知电容（C 2> 2）来建模所寻找的电容（C 1> 1）。

公开(公告)号：US08448119B1

公开(公告)日：2013-05-21

申请号：US13478127

申请日：2012-05-23

申请人： Rachel Gordin ,  David Goren

发明人： Rachel Gordin ,  David Goren

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5036 ,  G06F17/5068

摘要： A system and method for design and modeling of vertical interconnects for 3DI applications. A design and modeling methodology of vertical interconnects for 3DI applications includes models that represent the frequency dependent behavior of vertical interconnects by means of multi-segment RLC scalable filter networks. The networks allow for accuracy versus computation efficiency tradeoffs, while maintaining correct asymptotic behavior at both high and low frequency limits. In the framework of the model it is shown that a major effect is pronounced frequency dependent silicon substrate induced dispersion and loss effects, which is considered in through silicon via (TSV) parallel Y-element parameters, including capacitance and conductance.

摘要翻译： 用于3DI应用的垂直互连的设计和建模的系统和方法。 用于3DI应用的垂直互连的设计和建模方法包括通过多段RLC可伸缩滤波器网络表示垂直互连的频率相关行为的模型。 网络允许精度与计算效率的折衷，同时在高频和低频限制下保持正确的渐近行为。 在该模型的框架中，显示了主要影响是频率依赖性硅衬底诱导的色散和损耗效应，这在硅通孔（TSV）并联Y元件参数（包括电容和电导）中被考虑。