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    Topologies and Methodologies for AMS Integrated Circuit Design
    1.
    发明申请
    Topologies and Methodologies for AMS Integrated Circuit Design 有权
    AMS集成电路设计的拓扑和方法

    公开(公告)号：US20090150848A1

    公开(公告)日：2009-06-11

    申请号：US11927720

    申请日：2007-12-11

    申请人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Anatoly Sherman ,  Michael Zelikson

    发明人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Anatoly Sherman ,  Michael Zelikson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5063 ,  G06F2217/86

    摘要： A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines.

    摘要翻译： 用于模拟和混合信号电路的工具包括使得用户能够识别芯片架构中的一个或多个关键互连线和用于所述关键互连线的一个或多个可选择的预定义拓扑的单元。 每个拓扑包括一个或多个信号线和电流返回路径。 大部分电场线包含在拓扑的边界内。 本发明还包括一种用于设计模拟和混合信号（AMS）集成电路（IC）的方法，包括定义芯片架构和平面图，识别一个或多个关键互连线并且为关键互连选择预先设计的传输线拓扑 线条。

    Topologies and methodologies for AMS integrated circuit design
    3.
    发明授权
    Topologies and methodologies for AMS integrated circuit design 有权
    AMS集成电路设计的拓扑和方法

    公开(公告)号：US08347244B2

    公开(公告)日：2013-01-01

    申请号：US11927720

    申请日：2007-12-11

    申请人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Sherman Anatoly ,  Michael Zelikson

    发明人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Sherman Anatoly ,  Michael Zelikson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5063 ,  G06F2217/86

    摘要： A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines.

    摘要翻译： 用于模拟和混合信号电路的工具包括使得用户能够识别芯片架构中的一个或多个关键互连线和用于所述关键互连线的一个或多个可选择的预定义拓扑的单元。 每个拓扑包括一个或多个信号线和电流返回路径。 大部分电场线包含在拓扑的边界内。 本发明还包括一种用于设计模拟和混合信号（AMS）集成电路（IC）的方法，包括定义芯片架构和平面图，识别一个或多个关键互连线，并为关键互连选择预先设计的传输线拓扑 线条。

    Interconnect-aware integrated circuit design
    4.
    发明授权
    Interconnect-aware integrated circuit design 失效
    互连式集成电路设计

    公开(公告)号：US07080340B2

    公开(公告)日：2006-07-18

    申请号：US10723752

    申请日：2003-11-26

    申请人： David Goren ,  Rachel Gordin ,  Michael Zelikson

    发明人： David Goren ,  Rachel Gordin ,  Michael Zelikson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： In a system 10 for designing an integrated circuit, a preliminary design of the integrated circuit is defined and critical interconnect lines in the preliminary design are identified. Further, any critical interconnect lines which are affected by crossing lines in the preliminary design are identified, and a transmission line model 35 is defined to represent each critical interconnect line. A layout design of the integrated circuit, comprising circuit components and parameters thereof, is then defined using the preliminary design and the transmission line model 35 for each critical interconnect line. Component parameters are then extracted from the layout design for simulation of the design using the extracted component parameters. During this design process, for each transmission line model 35 representing a critical interconnect line affected by a crossing line, an environment terminal 36 is provided. The environment terminal 36 comprises a connection to the model 35 via at least one circuit component representing the effect of the crossing line on the model. The environment terminal 36 is connected to the appropriate crossing line in the integrated circuit design, whereby crossing line effects are accommodated in the design process.

    摘要翻译： 在用于设计集成电路的系统10中，定义了集成电路的初步设计，并且识别了初步设计中的关键互连线。 此外，识别在初步设计中受交叉线影响的任何关键互连线，并且传输线模型35被定义为表示每个关键互连线。 然后使用用于每个关键互连线的初步设计和传输线模型35来定义包括电路部件及其参数的集成电路的布局设计。 然后从布局设计中提取组件参数，以使用提取的组件参数进行设计的仿真。 在该设计过程中，对于表示受交叉线影响的关键互连线的每个传输线模型35，提供环境终端36。 环境终端36包括通过表示模型上的交叉线的影响的至少一个电路组件到模型35的连接。 环境端子36在集成电路设计中连接到适当的交叉线，由此在设计过程中容纳交叉线效应。

    Interconnect-aware integrated circuit design
    5.
    发明申请
    Interconnect-aware integrated circuit design 失效
    互连式集成电路设计

    公开(公告)号：US20050114819A1

    公开(公告)日：2005-05-26

    申请号：US10723752

    申请日：2003-11-26

    申请人： David Goren ,  Rachel Gordin ,  Michael Zelikson

    发明人： David Goren ,  Rachel Gordin ,  Michael Zelikson

    IPC分类号： G06F17/50 ,  G06F9/455 ,  H01L21/82

    CPC分类号： G06F17/5036

    摘要： In a system 10 for designing an integrated circuit, a preliminary design of the integrated circuit is defined and critical interconnect lines in the preliminary design are identified. Further, any critical interconnect lines which are affected by crossing lines in the preliminary design are identified, and a transmission line model 35 is defined to represent each critical interconnect line. A layout design of the integrated circuit, comprising circuit components and parameters thereof, is then defined using the preliminary design and the transmission line model 35 for each critical interconnect line. Component parameters are then extracted from the layout design for simulation of the design using the extracted component parameters. During this design process, for each transmission line model 35 representing a critical interconnect line affected by a crossing line, an environment terminal 36 is provided. The environment terminal 36 comprises a connection to the model 35 via at least one circuit component representing the effect of the crossing line on the model. The environment terminal 36 is connected to the appropriate crossing line in the integrated circuit design, whereby crossing line effects are accommodated in the design process.

    摘要翻译： 在用于设计集成电路的系统10中，定义了集成电路的初步设计，并且识别了初步设计中的关键互连线。 此外，识别在初步设计中受交叉线影响的任何关键互连线，并且传输线模型35被定义为表示每个关键互连线。 然后使用用于每个关键互连线的初步设计和传输线模型35来定义包括电路部件及其参数的集成电路的布局设计。 然后从布局设计中提取组件参数，以使用提取的组件参数进行设计的仿真。 在该设计过程中，对于表示受交叉线影响的关键互连线的每个传输线模型35，提供环境终端36。 环境终端36包括通过表示模型上的交叉线的影响的至少一个电路组件到模型35的连接。 环境端子36在集成电路设计中连接到适当的交叉线，由此在设计过程中容纳交叉线效应。

    Driver output swing control using a mirror driver
    6.
    发明授权
    Driver output swing control using a mirror driver 失效
    驱动器输出摆幅控制使用镜像驱动

    公开(公告)号：US06476649B1

    公开(公告)日：2002-11-05

    申请号：US09715423

    申请日：2000-11-17

    申请人： David Goren ,  Donald J Papae ,  Michael Zelikson

    发明人： David Goren ,  Donald J Papae ,  Michael Zelikson

    IPC分类号： H03K300

    CPC分类号： H03K17/14

    摘要： Instrumentation driver apparatus, including a main driver, coupled to receive an alternating input signal and having a main circuit structure, which is adapted to generate, in response to the alternating input signal, a main output signal with alternating voltage. The apparatus includes a mirror driver, coupled to receive a direct voltage input and having a mirror circuit structure located in proximity to the main circuit structure, which is adapted to generate a mirror output signal in response to the direct voltage input, such that a variation in an operating condition of the main driver causes a corresponding variation in the mirror output signal. The apparatus further includes a feedback circuit, coupled to receive the mirror output signal, which provides in response to the mirror output signal a feedback stabilization input to the main driver so as to stabilize the main output signal.

    摘要翻译： 包括主驱动器的仪表驱动器装置被耦合以接收交替输入信号并且具有主电路结构，其适于响应于交流输入信号而产生具有交变电压的主输出信号。 该装置包括镜驱动器，其被耦合以接收直接电压输入并且具有位于主电路结构附近的镜电路结构，其适于响应于直流电压输入而产生反射镜输出信号，使得变化 在主驱动器的操作状态下，镜像输出信号产生相应的变化。 该装置还包括一个反馈电路，被耦合以接收反射镜输出信号，其响应于反射镜输出信号提供反馈稳定输入到主驱动器，以便稳定主输出信号。

    METHODS AND SYSTEMS TO CONTROL POWER GATES DURING AN ACTIVE STATE OF A GATED DOMAIN BASED ON LOAD CONDITIONS OF THE GATED DOMAIN
    8.
    发明申请
    METHODS AND SYSTEMS TO CONTROL POWER GATES DURING AN ACTIVE STATE OF A GATED DOMAIN BASED ON LOAD CONDITIONS OF THE GATED DOMAIN 审中-公开
    基于浇注域的负载条件的浇注域的活动状态期间控制电网的方法和系统

    公开(公告)号：US20150149794A1

    公开(公告)日：2015-05-28

    申请号：US14350548

    申请日：2011-12-27

    申请人： Michael Zelikson ,  Vjekoslav Svilan ,  Norbert Unger ,  Shai Rotem

    发明人： Michael Zelikson ,  Vjekoslav Svilan ,  Norbert Unger ,  Shai Rotem

    IPC分类号： G06F1/26 ,  H03K17/687

    CPC分类号： G06F1/26 ,  G06F1/3243 ,  G06F1/3287 ,  H03K17/687 ,  Y02D10/152 ,  Y02D10/171

    摘要： Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.

    摘要翻译： 在电源选通电路的有效状态期间，响应于电路中的负载变化来调节电网和电网门控之间的电阻以维持相对一致的IR下降的方法和系统。 可以基于诸如电压的负载因子的变化来选择性地启用和禁用功率门（PG）的子集，其可以在门控配电网格处和/或接近电力门控电路中的晶体管栅极监视 。 可以执行调整以最小化所监视的电压和参考之间的差异，例如通过逐次逼近或CMS软件。 PG子集可以分布在集成电路（IC）裸片的一个或多个层内，并且可以基于位置被选择性地启用/禁用。 PG可以嵌入集成电路（IC）管芯的下层内，例如在IC管芯的金属层内。

    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING IMPROVED PROCESSOR CORE DEEP POWER DOWN EXIT LATENCY BY USING REGISTER SECONDARY UNINTERRUPTED POWER SUPPLY
    9.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING IMPROVED PROCESSOR CORE DEEP POWER DOWN EXIT LATENCY BY USING REGISTER SECONDARY UNINTERRUPTED POWER SUPPLY 有权
    方法，装置和能源节约系统，其中包括使用注册次级不间断电源改进处理器核心深度断电退出

    公开(公告)号：US20120166852A1

    公开(公告)日：2012-06-28

    申请号：US13335880

    申请日：2011-12-22

    申请人： Inder M. Sodhi ,  Alon Naveh ,  Michael Zelikson ,  Sanjeev S. Jahagirdar ,  Varghese George

    发明人： Inder M. Sodhi ,  Alon Naveh ,  Michael Zelikson ,  Sanjeev S. Jahagirdar ,  Varghese George

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3296 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D10/172

    摘要： Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be increased back to an active processor power state, the critical state data stored in the keeper circuits is written back to the critical state register latches.

    摘要翻译： 本发明的实施例涉及从计算设备处理器核心深度掉电来改善退出等待时间。 处理器状态数据可以在深度掉电模式期间通过提供第二不间断电压供应来始终保持驻留在处理器的关键状态寄存器内的保持器电路。 当这些寄存器接收到指示处理器电源状态将从活动处理器电源状态降低到零处理器电源状态的控制信号时，它们将临界状态数据从临界状态寄存器锁存器写入到所提供的保持器电路 不间断的电源。 然后，当寄存器接收到指示处理器的处理器电源状态将增加回到活动处理器功率状态的控制信号时，存储在保持器电路中的临界状态数据被写回到临界状态寄存器锁存器。