公开(公告)号：US07514964B2

公开(公告)日：2009-04-07

申请号：US11377935

申请日：2006-03-15

申请人： Amir Fijany ,  Farrokh Vatan ,  Kerem Akarvardar ,  Benjamin Blalock ,  Suheng Chen ,  Sorin Cristoloveanu ,  Elzbieta Kolawa ,  Mohammad M. Mojarradi ,  Nikzad Toomarian

发明人： Amir Fijany ,  Farrokh Vatan ,  Kerem Akarvardar ,  Benjamin Blalock ,  Suheng Chen ,  Sorin Cristoloveanu ,  Elzbieta Kolawa ,  Mohammad M. Mojarradi ,  Nikzad Toomarian

IPC分类号： H03K19/20 ,  G11C7/00

CPC分类号： H01L29/785 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/42384 ,  H01L2029/7857

摘要： An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

摘要翻译： 公开了一种基于G4-FET技术的通用和可编程逻辑门，从而设计出更高效的逻辑电路。 还介绍了一种基于G4-FET的全加器设计。 G4-FET还可以作为独特的路由器设备，提供彼此隔离和垂直的信号路径的共面交叉。 这有可能克服VLSI设计中的复杂互连方案变得越来越成问题的主要限制。

公开(公告)号：US20070008013A1

公开(公告)日：2007-01-11

申请号：US11377935

申请日：2006-03-15

申请人： Amir Fijany ,  Farrokh Vatan ,  Kerem Akarvardar ,  Benjamin Blalock ,  Suheng Chen ,  Sorin Cristoloveanu ,  Elzbieta Kolawa ,  Mohammad Mojarradi ,  Nikzad Toomarian

发明人： Amir Fijany ,  Farrokh Vatan ,  Kerem Akarvardar ,  Benjamin Blalock ,  Suheng Chen ,  Sorin Cristoloveanu ,  Elzbieta Kolawa ,  Mohammad Mojarradi ,  Nikzad Toomarian

IPC分类号： H03K19/20

CPC分类号： H01L29/785 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/42384 ,  H01L2029/7857

摘要： An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

摘要翻译： 公开了一种基于GOS-4FET技术的通用和可编程逻辑门，从而设计出更有效的逻辑电路。 还提出了一种基于G_FET 4FET的新的全加器设计。 也可以用作独特的路由器设备，提供彼此隔离和垂直的信号路径的共面交叉。 这有可能克服VLSI设计中的复杂互连方案变得越来越成问题的主要限制。

公开(公告)号：US08010591B2

公开(公告)日：2011-08-30

申请号：US11804893

申请日：2007-05-21

申请人： Mohammad M. Mojarradi ,  Benjamin Blalock ,  Sorin Cristoloveanu ,  Suheng Chen ,  Kerem Akarvardar

发明人： Mohammad M. Mojarradi ,  Benjamin Blalock ,  Sorin Cristoloveanu ,  Suheng Chen ,  Kerem Akarvardar

IPC分类号： G06E3/00

CPC分类号： G06G7/16

摘要： A differential output analog multiplier circuit utilizing four G4-FETs, each source connected to a current source. The four G4-FETs may be grouped into two pairs of two G4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

摘要翻译： 使用四个G4-FET的差分输出模拟乘法器电路，每个源极连接到电流源。 四个G4-FET可以分成两对，每对两个G4-FET，其中一对具有连接到负载的漏极，另一对的漏极连接到另一个负载。 差分输出电压在两个负载下进行。 在一个实施例中，对于每个G4-FET，第一和第二结门各自连接在一起，其中第一输入电压施加到每对的前门，并且第二输入电压施加到每个的第一结门 对。 描述和要求保护其他实施例。

公开(公告)号：US20080001658A1

公开(公告)日：2008-01-03

申请号：US11804893

申请日：2007-05-21

申请人： Mohammad Mojarradi ,  Benjamin Blalock ,  Sorin Cristoloveanu ,  Suheng Chen ,  Kerem Akarvardar

发明人： Mohammad Mojarradi ,  Benjamin Blalock ,  Sorin Cristoloveanu ,  Suheng Chen ,  Kerem Akarvardar

IPC分类号： H99Z99/00

CPC分类号： G06G7/16

摘要： A differential output analog multiplier circuit utilizing four G4-FETs, each source connected to a current source. The four G4-FETs may be grouped into two pairs of two G4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

摘要翻译： 一个差分输出模拟乘法器电路，利用四个四极管，每个源极连接到电流源。 四个G 4 SFET可以被分组成两对两个两个G 4 -FET，其中一对具有连接到负载的漏极，另一对具有 其下水道连接到另一个负载。 差分输出电压在两个负载下进行。 在一个实施例中，对于每个G 4 -FET，第一和第二结门各自连接在一起，其中第一输入电压施加到每对的前栅极，第二输入电压为 应用于每对的第一个结门。 描述和要求保护其他实施例。

公开(公告)号：US20070229158A1

公开(公告)日：2007-10-04

申请号：US11636365

申请日：2006-12-07

申请人： Mohammad Mojarradi ,  Greg Levanas ,  Yuan Chen ,  Raymond Cozy ,  Robert Greenwell ,  Stephen Terry ,  Benjamin Blalock

发明人： Mohammad Mojarradi ,  Greg Levanas ,  Yuan Chen ,  Raymond Cozy ,  Robert Greenwell ,  Stephen Terry ,  Benjamin Blalock

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  H03F1/30 ,  H03F1/301 ,  H03F3/45183 ,  H03F3/45632 ,  H03F2200/447 ,  H03F2203/45138 ,  H03F2203/45652

摘要： The present invention relates to a reference current circuit. The reference circuit comprises a low-level current bias circuit, a voltage proportional-to-absolute temperature generator for creating a proportional-to-absolute temperature voltage (VPTAT), and a MOSFET-based constant-IC regulator circuit. The MOSFET-based constant-IC regulator circuit includes a constant-IC input and constant-IC output. The constant-IC input is electrically connected with the VPTAT generator such that the voltage proportional-to-absolute temperature is the input into the constant-IC regulator circuit. Thus the constant-IC output maintains the constant-IC ratio across any temperature range.

摘要翻译： 本发明涉及参考电流电路。 参考电路包括一个低电平电流偏置电路，一个用于产生比例绝对温度电压（VPTAT）的电压比例绝对温度发生器，以及一个基于MOSFET的恒定IC稳压电路。 基于MOSFET的恒定IC稳压电路包括恒定IC输入和恒定IC输出。 恒定IC输入与VPTAT发生器电连接，使得电压成正比绝对温度是恒定IC调节器电路的输入。 因此，恒定IC输出在任何温度范围内保持恒定IC比。

公开(公告)号：US06503782B2

公开(公告)日：2003-01-07

申请号：US09796490

申请日：2001-03-02

申请人： Jeffrey Blaine Casady ,  Benjamin Blalock ,  Stephen E. Saddow ,  Michael S. Mazzola

发明人： Jeffrey Blaine Casady ,  Benjamin Blalock ,  Stephen E. Saddow ,  Michael S. Mazzola

IPC分类号： H01L21332

CPC分类号： H01L29/66068 ,  H01L27/098 ,  H01L29/1608 ,  H01L29/66901 ,  H01L29/808

摘要： A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the produced devices may have pinchoff voltages of either positive or negative polarities. A first layer of either p-type or n-type is formed as a base. An alternating, channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer. Etching is used to provide contacts for the gates, source, and drain of the device. In one variation, pinchoff voltage is controlled via dopant level and thickness the channel region. In another variation, pinchoff voltage is controlled by variation of dopant level across the channel layer; and in another variation, pinchoff voltage is controlled by both thickness and variation of dopant level.