公开(公告)号：US20070008013A1

公开(公告)日：2007-01-11

申请号：US11377935

申请日：2006-03-15

申请人： Amir Fijany ,  Farrokh Vatan ,  Kerem Akarvardar ,  Benjamin Blalock ,  Suheng Chen ,  Sorin Cristoloveanu ,  Elzbieta Kolawa ,  Mohammad Mojarradi ,  Nikzad Toomarian

发明人： Amir Fijany ,  Farrokh Vatan ,  Kerem Akarvardar ,  Benjamin Blalock ,  Suheng Chen ,  Sorin Cristoloveanu ,  Elzbieta Kolawa ,  Mohammad Mojarradi ,  Nikzad Toomarian

IPC分类号： H03K19/20

CPC分类号： H01L29/785 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/42384 ,  H01L2029/7857

摘要： An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

摘要翻译： 公开了一种基于GOS-4FET技术的通用和可编程逻辑门，从而设计出更有效的逻辑电路。 还提出了一种基于G_FET 4FET的新的全加器设计。 也可以用作独特的路由器设备，提供彼此隔离和垂直的信号路径的共面交叉。 这有可能克服VLSI设计中的复杂互连方案变得越来越成问题的主要限制。

公开(公告)号：US07514964B2

公开(公告)日：2009-04-07

申请号：US11377935

申请日：2006-03-15

申请人： Amir Fijany ,  Farrokh Vatan ,  Kerem Akarvardar ,  Benjamin Blalock ,  Suheng Chen ,  Sorin Cristoloveanu ,  Elzbieta Kolawa ,  Mohammad M. Mojarradi ,  Nikzad Toomarian

发明人： Amir Fijany ,  Farrokh Vatan ,  Kerem Akarvardar ,  Benjamin Blalock ,  Suheng Chen ,  Sorin Cristoloveanu ,  Elzbieta Kolawa ,  Mohammad M. Mojarradi ,  Nikzad Toomarian

IPC分类号： H03K19/20 ,  G11C7/00

CPC分类号： H01L29/785 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/42384 ,  H01L2029/7857

摘要： An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

摘要翻译： 公开了一种基于G4-FET技术的通用和可编程逻辑门，从而设计出更高效的逻辑电路。 还介绍了一种基于G4-FET的全加器设计。 G4-FET还可以作为独特的路由器设备，提供彼此隔离和垂直的信号路径的共面交叉。 这有可能克服VLSI设计中的复杂互连方案变得越来越成问题的主要限制。

公开(公告)号：US5508538A

公开(公告)日：1996-04-16

申请号：US161908

申请日：1993-11-30

申请人： Amir Fijany ,  Jacob Barhen ,  Nikzad Toomarian

发明人： Amir Fijany ,  Jacob Barhen ,  Nikzad Toomarian

IPC分类号： G06F17/16 ,  G06N3/063 ,  H01L29/76 ,  G06G7/00 ,  G11C19/18 ,  H01L27/148

CPC分类号： G06F17/16 ,  G06N3/063

摘要： The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

公开(公告)号：US5680515A

公开(公告)日：1997-10-21

申请号：US534537

申请日：1995-09-27

申请人： Jacob Barhen ,  Nikzad Toomarian ,  Amir Fijany ,  Michail Zak

发明人： Jacob Barhen ,  Nikzad Toomarian ,  Amir Fijany ,  Michail Zak

IPC分类号： G06F17/16 ,  G06N3/063 ,  G06F15/00

CPC分类号： G06F17/16 ,  G06N3/063

摘要： The present invention enhances the bit resolution of a CCD/CID MVM processor by storing each bit of each matrix element as a separate CCD charge packet. The bits of each input vector are separately multiplied by each bit of each matrix element in massive parallelism and the resulting products are combined appropriately to synthesize the correct product. In another aspect of the invention, such arrays are employed in a pseudo-spectral method of the invention, in which partial differential equations are solved by expressing each derivative analytically as matrices, and the state function is updated at each computation cycle by multiplying it by the matrices. The matrices are treated as synaptic arrays of a neural network and the state function vector elements are treated as neurons. In a further aspect of the invention, moving target detection is performed by driving the soliton equation with a vector of detector outputs. The neural architecture consists of two synaptic arrays corresponding to the two differential terms of the soliton-equation and an adder connected to the output thereof and to the output of the detector array to drive the soliton equation.

摘要翻译： 本发明通过将每个矩阵元素的每个比特存储为单独的CCD电荷分组来增强CCD / CID MVM处理器的比特分辨率。 每个输入向量的位分别乘以每个矩阵元素的每个比特的大规模并行性，并将所得到的乘积合并以合成正确的乘积。 在本发明的另一方面，这种阵列用于本发明的伪光谱方法，其中通过将每个导数分析地表示为矩阵来求解偏微分方程，并且通过将每个计算周期的状态函数乘以 矩阵。 矩阵被视为神经网络的突触阵列，状态函数向量元素被视为神经元。 在本发明的另一方面，通过用检测器输出的向量驱动孤子方程来执行移动目标检测。 神经体系结构由两个突变阵列组成，这两个突触阵列对应于孤子方程的两个微分项，以及连接到其输出的加法器和检测器阵列的输出以驱动孤子方程。

公开(公告)号：US5952685A

公开(公告)日：1999-09-14

申请号：US598900

申请日：1996-02-09

申请人： Amir Fijany ,  Jacob Barhen ,  Nikzad Toomarian

发明人： Amir Fijany ,  Jacob Barhen ,  Nikzad Toomarian

IPC分类号： G06F17/16 ,  G06N3/063 ,  H01L29/76 ,  G06G7/00 ,  G11C19/18 ,  H01L27/148

CPC分类号： G06F17/16 ,  G06N3/063

摘要： The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

摘要翻译： 本发明体现在能够在O（1）中并行地在多个CCD / CID阵列中通过同时进行矩阵矢量乘法（MVM）运算的傅里叶变换的电荷耦合器件（CCD）/电荷注入器件（CID） 脚步。 例如，在一个实施例中，第一CCD / CID阵列基于哈特利变换的置换来存储表示第一矩阵运算符的电荷分组，并计算输入向量的傅里叶变换。 基于哈特利变换的不同排列，第二CCD / CID阵列存储表示第二矩阵运算符的电荷分组，并计算进入矢量的傅里叶变换。 输入矢量同时应用于两个CCD / CID阵列的输入，傅立叶变换的实部和虚部在CCD / CID阵列中执行单个MVM操作所需的时间内同时产生。

公开(公告)号：US5491650A

公开(公告)日：1996-02-13

申请号：US49829

申请日：1993-04-19

申请人： Jacob Barhen ,  Nikzad Toomarian ,  Amir Fijany ,  Michail Zak

发明人： Jacob Barhen ,  Nikzad Toomarian ,  Amir Fijany ,  Michail Zak

IPC分类号： G06F17/16 ,  G06N3/063 ,  G06J1/00 ,  G06F7/52

CPC分类号： G06F17/16 ,  G06N3/063

摘要： The present invention discloses increased bit resolution of a charge coupled device (CCD)/charge injection device (CID) matrix vector multiplication (MVM) processor by storing each bit of each matrix element as a separate CCD charge packet. The bits of each input vector are separately multiplied by each bit of each matrix element in massive parallelism and the resulting products are combined appropriately to synthesize the correct product. In addition, such arrays are employed in a pseudo-spectral method of the invention, in which partial differential equations are solved by expressing each derivative analytically as matrices, and the state function is updated at each computation cycle by multiplying it by the matrices. The matrices are treated as synaptic arrays of a neutral network and the state function vector elements are treated as neurons. Further, moving target detection is performed by driving the soliton equation with a vector of detector outputs. The neural architecture consists of two synaptic arrays corresponding to the two differential terms of the soliton equation and an adder connected to the output thereof and to the output of the detector array to drive the soliton equation.

摘要翻译： 本发明通过将每个矩阵元素的每一位存储为单独的CCD电荷包，提高了电荷耦合器件（CCD）/电荷注入器件（CID）矩阵矢量乘法（MVM）处理器的位分辨率。 每个输入向量的位分别乘以每个矩阵元素的每个比特的大规模并行性，并将所得到的乘积合并以合成正确的乘积。 此外，在本发明的伪光谱方法中采用这样的阵列，其中通过将每个导数分析地表示为矩阵来求解偏微分方程，并且通过将其乘以矩阵在每个计算周期更新状态函数。 矩阵被视为中性网络的突触阵列，状态函数向量元素被视为神经元。 此外，通过用检测器输出的向量驱动孤子方程来执行移动目标检测。 神经结构由两个对应于孤子方程的两个微分项的突触阵列和连接到其输出的加法器和检测器阵列的输出驱动孤子方程组成。

公开(公告)号：US08521487B2

公开(公告)日：2013-08-27

申请号：US13041644

申请日：2011-03-07

申请人： Amir Fijany ,  Farrokh Vatan

发明人： Amir Fijany ,  Farrokh Vatan

IPC分类号： G06F7/60 ,  G06F17/10 ,  G06F17/50

CPC分类号： G06F17/5018 ,  G06F11/3608

摘要： A method for generating a minimal set of Analytical Redundancy Relations representing a system to which a plurality of sensors is associated for the observation of variables indicative of operating conditions and adapted to enable detection and isolation of faults. The minimal set of Analytical Redundancy Relations is derived from a complete set of Analytical Redundancy Relations in implicit form, for which an associated binary Fault Signature Matrix is specified, and comprises the relations associated to a minimal subset of rows of the original matrix, which has the same number of non-zero columns and the same number of distinct columns as the original matrix.

摘要翻译： 一种生成分析冗余关系的最小集合的方法，其表示多个传感器相关联的系统，用于观察指示操作条件的变量，并适于使能检测和隔离故障。 分析冗余关系的最小集合是从隐式形式的一组完整的分析冗余关系导出的，为此分配冗余关系被指定为相关联的二进制故障签名矩阵，并且包括与原始矩阵的最小子集相关联的关系，其具有 与原始矩阵相同数量的非零列和相同数量的不同列。

公开(公告)号：US20110022891A1

公开(公告)日：2011-01-27

申请号：US12841691

申请日：2010-07-22

申请人： Amir Fijany ,  Anthony Barrett ,  Farrokh Vatan

发明人： Amir Fijany ,  Anthony Barrett ,  Farrokh Vatan

IPC分类号： G06F11/07

CPC分类号： G06F11/3608

摘要： A method for the generation of a set of conflicts for model-based system diagnostics is described, with which system a plurality of sensors is associated for the observation of variables indicative of operation conditions.The method starts from generating a complete set of Analytical Redundancy Relations (ARRs) in implicit form and, for each diagnosis instance: it performs a system simulation, computing the expected values for a first subset of Analytical Redundancy Relations (D-ARRs) including the relations involving only one system observation variable; it compares the expected and observed values of the system observation variables to identify the inconsistent variables, i.e. the unsatisfied redundancy relations, indicating a fault in at least one system component; and, when discrepancies are detected, it checks the consistency of each relation belonging to a second subset of Analytical Redundancy Relations (I-ARR), comprising relations involving a plurality of system observation variables, at least one of which exhibits discrepancies between expected and observed values; therefore identifying the support set of the unsatisfied Redundancy Relations as set of system conflicts.

摘要翻译： 描述了用于产生用于基于模型的系统诊断的一组冲突的方法，与该系统相关联的多个传感器用于观察指示操作条件的变量。 该方法从隐式形式生成一套完整的分析冗余关系（ARR）开始，对于每个诊断实例，它执行系统仿真，计算分析冗余关系（D-ARR）的第一个子集的期望值，包括 只涉及一个系统观测变量的关系; 它比较系统观测变量的预期值和观测值，以识别指示至少一个系统组件中的故障的不一致变量，即不满足的冗余度关系; 并且当检测到差异时，它检查属于分析冗余关系（I-ARR）的第二子集的每个关系的一致性，其包括涉及多个系统观察变量的关系，其中至少一个呈现预期和观察到的差异 价值观 因此，将不满意​​的冗余关系的支持集确定为系统冲突。

公开(公告)号：US08775124B2

公开(公告)日：2014-07-08

申请号：US12717798

申请日：2010-03-04

申请人： Amir Fijany ,  Farrokh Vatan

发明人： Amir Fijany ,  Farrokh Vatan

IPC分类号： G01R31/00 ,  G06F11/08

CPC分类号： G06F17/10 ,  G05B23/0254

摘要： A method for generating a set of analytical redundancy relations representative of a system with which a plurality of sensors is associated for the observation of variables indicative of operating conditions and adapted to enable detection and discrimination of faults. A complete set of analytical redundancy relations of the system is built from a set of intermediate relations established between observable and non-observable variables of the system, wherein each intermediate relation is generated by combining two predetermined relations Rj, Rk, each of which is expressed in an implicit form as a tuple (i) of a subset Sj of system variables, (ii) of the set Cj of the support components for said relation, and (iii) of the set Tj of the primary relations used to derive said intermediate relation.

摘要翻译： 一种用于生成表示与多个传感器相关联的系统的分析冗余关系的集合的方法，用于观察指示操作条件的变量并适于使能检测和辨别故障。 系统的一组完整的分析冗余关系由系统可观测和不可观测变量之间建立的一组中间关系构成，其中每个中间关系是通过组合两个预定关系Rj，Rk， 作为系统变量的子集Sj的元组（i）的隐式形式，（ii）用于所述关系的支持组件的集合Cj，以及（iii）用于导出所述中间件的主要关系的集合Tj 关系。

公开(公告)号：US08311783B2

公开(公告)日：2012-11-13

申请号：US12841691

申请日：2010-07-22

申请人： Amir Fijany ,  Anthony Barrett ,  Farrokh Vatan

发明人： Amir Fijany ,  Anthony Barrett ,  Farrokh Vatan

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F11/07

CPC分类号： G06F11/3608

摘要： A method for the generation of a set of conflicts for model-based system diagnostics is described, with which system a plurality of sensors is associated for the observation of variables indicative of operation conditions.The method starts from generating a complete set of Analytical Redundancy Relations (ARRs) in implicit form and, for each diagnosis instance: it performs a system simulation, computing the expected values for a first subset of Analytical Redundancy Relations (D-ARRs) including the relations involving only one system observation variable; it compares the expected and observed values of the system observation variables to identify the inconsistent variables, i.e. the unsatisfied redundancy relations, indicating a fault in at least one system component; and, when discrepancies are detected, it checks the consistency of each relation belonging to a second subset of Analytical Redundancy Relations (I-ARR), comprising relations involving a plurality of system observation variables, at least one of which exhibits discrepancies between expected and observed values; therefore identifying the support set of the unsatisfied Redundancy Relations as set of system conflicts.

摘要翻译： 描述了用于产生用于基于模型的系统诊断的一组冲突的方法，与该系统相关联的多个传感器用于观察指示操作条件的变量。 该方法从隐式形式生成一套完整的分析冗余关系（ARR）开始，对于每个诊断实例，它执行系统仿真，计算分析冗余关系（D-ARR）的第一个子集的期望值，包括 只涉及一个系统观测变量的关系; 它比较系统观测变量的预期值和观测值，以识别指示至少一个系统组件中的故障的不一致变量，即不满足的冗余度关系; 并且当检测到差异时，它检查属于分析冗余关系（I-ARR）的第二子集的每个关系的一致性，其包括涉及多个系统观察变量的关系，其中至少一个呈现预期和观察到的差异 价值观 因此，将不满意​​的冗余关系的支持集确定为系统冲突。