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    Four-gate transistor analog multiplier circuit
    3.
    发明授权
    Four-gate transistor analog multiplier circuit 有权
    四门晶体管模拟乘法电路

    公开(公告)号：US08010591B2

    公开(公告)日：2011-08-30

    申请号：US11804893

    申请日：2007-05-21

    申请人： Mohammad M. Mojarradi ,  Benjamin Blalock ,  Sorin Cristoloveanu ,  Suheng Chen ,  Kerem Akarvardar

    发明人： Mohammad M. Mojarradi ,  Benjamin Blalock ,  Sorin Cristoloveanu ,  Suheng Chen ,  Kerem Akarvardar

    IPC分类号： G06E3/00

    CPC分类号： G06G7/16

    摘要： A differential output analog multiplier circuit utilizing four G4-FETs, each source connected to a current source. The four G4-FETs may be grouped into two pairs of two G4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

    摘要翻译： 使用四个G4-FET的差分输出模拟乘法器电路，每个源极连接到电流源。 四个G4-FET可以分成两对，每对两个G4-FET，其中一对具有连接到负载的漏极，另一对的漏极连接到另一个负载。 差分输出电压在两个负载下进行。 在一个实施例中，对于每个G4-FET，第一和第二结门各自连接在一起，其中第一输入电压施加到每对的前门，并且第二输入电压施加到每个的第一结门 对。 描述和要求保护其他实施例。

    Four-gate transistor analog multiplier circuit
    4.
    发明申请
    Four-gate transistor analog multiplier circuit 有权
    四门晶体管模拟乘法电路

    公开(公告)号：US20080001658A1

    公开(公告)日：2008-01-03

    申请号：US11804893

    申请日：2007-05-21

    申请人： Mohammad Mojarradi ,  Benjamin Blalock ,  Sorin Cristoloveanu ,  Suheng Chen ,  Kerem Akarvardar

    发明人： Mohammad Mojarradi ,  Benjamin Blalock ,  Sorin Cristoloveanu ,  Suheng Chen ,  Kerem Akarvardar

    IPC分类号： H99Z99/00

    CPC分类号： G06G7/16

    摘要： A differential output analog multiplier circuit utilizing four G4-FETs, each source connected to a current source. The four G4-FETs may be grouped into two pairs of two G4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

    摘要翻译： 一个差分输出模拟乘法器电路，利用四个四极管，每个源极连接到电流源。 四个G 4 SFET可以被分组成两对两个两个G 4 -FET，其中一对具有连接到负载的漏极，另一对具有 其下水道连接到另一个负载。 差分输出电压在两个负载下进行。 在一个实施例中，对于每个G 4 -FET，第一和第二结门各自连接在一起，其中第一输入电压施加到每对的前栅极，第二输入电压为 应用于每对的第一个结门。 描述和要求保护其他实施例。

    Multilevel memory device
    5.
    发明授权
    Multilevel memory device 有权
    多级存储器件

    公开(公告)号：US09019760B2

    公开(公告)日：2015-04-28

    申请号：US13304531

    申请日：2011-11-25

    申请人： Alexandre Hubert ,  Maryline Bawedin ,  Sorin Cristoloveanu ,  Thomas Ernst

    发明人： Alexandre Hubert ,  Maryline Bawedin ,  Sorin Cristoloveanu ,  Thomas Ernst

    IPC分类号： G11C11/40 ,  H01L27/108 ,  H01L29/792 ,  B82Y10/00 ,  H01L21/28 ,  H01L27/115 ,  H01L29/06

    CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/0665 ,  H01L29/0673

    摘要： A memory device is provided, including a back gate including a first portion of electrically conductive material, a first portion of dielectric material arranged on the back gate, a semiconductor nanobeam arranged on the first portion of dielectric material, a second portion of dielectric material covering the semiconductor nanobeam, a portion of material configured to receive electrons and holes, and configured to store electrical charges and covering the second portion of dielectric material, a third portion of dielectric material covering the portion of material configured to perform storage of electrical charges, and a front gate including a second portion of electrically conductive material covering the third portion of dielectric material.

    摘要翻译： 提供了一种存储器件，包括一个包括导电材料的第一部分的背栅，布置在背栅上的介质材料的第一部分，布置在电介质材料第一部分上的半导体纳米结构体，覆盖电介质材料的第二部分 半导体纳米结构体，被配置为接收电子和空穴并被配置为存储电荷并覆盖电介质材料的第二部分的材料的一部分，覆盖被配置为执行电荷存储的材料部分的介电材料的第三部分，以及 前门，其包括覆盖电介质材料的第三部分的导电材料的第二部分。

    Apparatus and methods of using second harmonic generation as a non-invasive optical probe for interface properties in layered structures
    6.
    发明申请
    Apparatus and methods of using second harmonic generation as a non-invasive optical probe for interface properties in layered structures 有权
    使用二次谐波生成作为非侵入性光学探针的分层结构中的界面特性的装置和方法

    公开(公告)号：US20060044641A1

    公开(公告)日：2006-03-02

    申请号：US11019906

    申请日：2004-12-21

    申请人： Michael Alles ,  Norman Tolk ,  Bongim Jun ,  Robert Pasternak ,  Ron Schrimpf ,  Sorin Cristoloveanu

    发明人： Michael Alles ,  Norman Tolk ,  Bongim Jun ,  Robert Pasternak ,  Ron Schrimpf ,  Sorin Cristoloveanu

    IPC分类号： G02F2/02

    CPC分类号： G01N21/63 ,  G01N21/55

    摘要： A method for non-invasively probing at least one interface property in a layered structure having at least one interface. In one embodiment, the method includes the steps of exposing the layered structure to an incident photon beam at an incident angle to produce a reflection beam, measuring intensities of the second harmonic generation signals from the reflection beam, and identifying an initial second harmonic generation intensity and a time evolution of second harmonic generation intensity from the measured second harmonic generation intensities so as to determine the at least one interface property of the layered structure.

    摘要翻译： 一种用于在具有至少一个接口的分层结构中非侵入性探测至少一个接口属性的方法。 在一个实施例中，该方法包括如下步骤：以入射角将入射光子束暴露于入射光子束以产生反射光束，测量来自反射光束的二次谐波产生信号的强度，以及识别初始二次谐波发生强度 以及从所测量的二次谐波发生强度的二次谐波发生强度的时间演变，以便确定层状结构的至少一个界面性质。

    MULTILEVEL MEMORY DEVICE
    7.
    发明申请
    MULTILEVEL MEMORY DEVICE 有权
    多媒体存储设备

    公开(公告)号：US20120134206A1

    公开(公告)日：2012-05-31

    申请号：US13304531

    申请日：2011-11-25

    申请人： Alexandre Hubert ,  Maryline Bawedin ,  Sorin Cristoloveanu ,  Thomas Ernst

    发明人： Alexandre Hubert ,  Maryline Bawedin ,  Sorin Cristoloveanu ,  Thomas Ernst

    IPC分类号： G11C11/34 ,  H01L29/792

    CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/0665 ,  H01L29/0673

    摘要： A memory device comprising: a back gate including a first portion of electrically conductive material, a first portion of dielectric material arranged on the back gate, a semiconductor nanobeam arranged on the first portion of dielectric material, a second portion of dielectric material covering the semiconductor nanobeam, a portion of material capable of receiving electrons and holes, and able to perform storage of electrical charges and covering the second portion of dielectric material, a third portion of dielectric material covering the portion of material capable of performing storage of electrical charges, a front gate including a second portion of electrically conductive material covering the third portion of dielectric material.

    摘要翻译： 一种存储器件，包括：背栅，其包括导电材料的第一部分，布置在所述背栅上的介电材料的第一部分，布置在所述介电材料的第一部分上的半导体纳米结构体，覆盖所述半导体的介电材料的第二部分 nanobeam，能够接收电子和空穴的材料的一部分，并且能够执行电荷的存储并覆盖介电材料的第二部分;覆盖能够执行电荷存储的材料部分的介电材料的第三部分， 前门包括覆盖电介质材料的第三部分的导电材料的第二部分。

    Z2FET field-effect transistor with a vertical subthreshold slope and with no impact ionization
    8.
    发明授权
    Z2FET field-effect transistor with a vertical subthreshold slope and with no impact ionization 有权
    Z2FET场效应晶体管具有垂直亚阈值斜率并且没有电击

    公开(公告)号：US08581310B2

    公开(公告)日：2013-11-12

    申请号：US13611841

    申请日：2012-09-12

    申请人： Jing Wan ,  Sorin Cristoloveanu ,  Cyrille Le Royer ,  Alexander Zaslavsky

    发明人： Jing Wan ,  Sorin Cristoloveanu ,  Cyrille Le Royer ,  Alexander Zaslavsky

    IPC分类号： H01L29/80

    CPC分类号： H01L29/808 ,  H01L29/407 ,  H01L29/7391 ,  H01L29/78696

    摘要： The transistor comprises first and second source/drain electrodes formed in a semiconductor film by N-doped and P-doped areas, respectively. A polarization voltage is applied between the two source/drain electrodes in order to impose to the P-doped electrode a potential higher than that of the N-doped electrode. The transistor comprises first and second devices for generating a potential barrier in the semiconductor film. The two potential barriers are opposed to the passage of the charge carriers emitted by the first and second source/drain electrodes, respectively. The two potential barriers are shifted with respect to an axis connecting the two source/drain electrodes. The two devices for generating a potential barrier are configured to generate a potential barrier having a variable amplitude and it are electrically connected to the gate and to the counter electrode.

    摘要翻译： 晶体管包括分别由N掺杂和P掺杂区域形成在半导体膜中的第一和第二源/漏电极。 在两个源/漏电极之间施加极化电压，以便向P掺杂电极施加比N掺杂电极高的电位。 晶体管包括用于在半导体膜中产生势垒的第一和第二器件。 两个势垒分别与由第一和第二源极/漏极发射的电荷载流子相通。 两个势垒相对于连接两个源极/漏极的轴移动。 用于产生势垒的两个器件被配置为产生具有可变幅度的势垒，并且其电连接到栅极和对电极。