公开(公告)号：US20130326200A1

公开(公告)日：2013-12-05

申请号：US13982854

申请日：2011-02-11

申请人： Amir Kleen ,  Itzhak Barak ,  Yuval Peled ,  Idan Rozenberg ,  Doron Schupper

发明人： Amir Kleen ,  Itzhak Barak ,  Yuval Peled ,  Idan Rozenberg ,  Doron Schupper

IPC分类号： G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861

摘要： An integrated circuit device comprising at least one instruction processing module arranged to compare validation data with data stored within a target register upon receipt of a load validation instruction. Wherein, the instruction processing module is further arranged to proceed with execution of a next sequential instruction if the validation data matches the stored data within the target register, and to load the validation data into the target register if the validation data does not match the stored data within the target register.

摘要翻译： 一种集成电路装置，包括至少一个指令处理模块，其被布置为在接收到负载验证指令时将验证数据与存储在目标寄存器内的数据进行比较。 其中，所述指令处理模块还被布置成如果所述验证数据与所述目标寄存器中存储的数据匹配，则继续执行下一个顺序指令，并且如果所述验证数据与所存储的所述存储的数据不匹配，则将所述验证数据加载到所述目标寄存器中 目标寄存器内的数据。

公开(公告)号：US08266414B2

公开(公告)日：2012-09-11

申请号：US12194286

申请日：2008-08-19

申请人： Lev Vaskevich ,  Itzhak Barak ,  Amir Paran ,  Yuval Peled ,  Idan Rozenberg ,  Doron Schupper

发明人： Lev Vaskevich ,  Itzhak Barak ,  Amir Paran ,  Yuval Peled ,  Idan Rozenberg ,  Doron Schupper

IPC分类号： G06F9/40

CPC分类号： G06F9/325 ,  G06F9/381

摘要： A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and (iii) selecting, during iterations of the instruction loop, whether to provide to a dispatch unit one of the first instructions of the instruction loop or another instruction that is fetched by the fetch unit; wherein the first instructions of the instruction loop are stored at the dispatch unit.

摘要翻译： 一种用于管理硬件指令循环的方法，所述方法包括：（i）由分支预测单元检测指令循环; 其中所述指令循环的大小超过在用于存储获取的指令的获取单元中分配的存储空间的大小; （ii）从提取单元请求获取遵循指令循环的第一指令的指令循环的指令; 以及（iii）在所述指令循环的迭代期间选择是否向所述调度单元提供所述指令循环的所述第一指令之一或由所述提取单元获取的另一指令; 其中指令循环的第一指令被存储在调度单元中。

公开(公告)号：US20130290686A1

公开(公告)日：2013-10-31

申请号：US13977082

申请日：2011-01-21

申请人： Yuval Peled ,  Itzhak Barak ,  Idan Rozenberg ,  Doron Schupper ,  Lev Vaskevich

发明人： Yuval Peled ,  Itzhak Barak ,  Idan Rozenberg ,  Doron Schupper ,  Lev Vaskevich

IPC分类号： G06F9/30 ,  G06F7/57

CPC分类号： G06F9/3001 ,  G06F7/57 ,  G06F9/30029 ,  G06F9/30072 ,  G06F9/30094

摘要： An integrated circuit device comprises at least one instruction processing module arranged to perform branch predication. The at least one instruction processing module comprises at least one predicate calculation module arranged to receive as an input at least one result vector for a predicate function and at least one conditional parameter value therefor and output a predicate result value from the at least one result vector based at least partly on the at least one received conditional parameter value.

摘要翻译： 集成电路装置包括布置成执行分支预测的至少一个指令处理模块。 所述至少一个指令处理模块包括至少一个谓词计算模块，被布置为接收用于谓词函数的至少一个结果向量作为输入，以及至少一个条件参数值，并从所述至少一个结果向量输出谓词结果值 至少部分地基于所述至少一个接收到的条件参数值。

公开(公告)号：US20100049958A1

公开(公告)日：2010-02-25

申请号：US12194286

申请日：2008-08-19

申请人： Lev Vaskevich ,  Itzhak Barak ,  Amir Paran ,  Yuval Peled ,  Idan Rozenberg ,  Doron Schupper

发明人： Lev Vaskevich ,  Itzhak Barak ,  Amir Paran ,  Yuval Peled ,  Idan Rozenberg ,  Doron Schupper

IPC分类号： G06F9/30

CPC分类号： G06F9/325 ,  G06F9/381

摘要： A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and (iii) selecting, during iterations of the instruction loop, whether to provide to a dispatch unit one of the first instructions of the instruction loop or another instruction that is fetched by the fetch unit; wherein the first instructions of the instruction loop are stored at the dispatch unit.

摘要翻译： 一种用于管理硬件指令循环的方法，所述方法包括：（i）由分支预测单元检测指令循环; 其中所述指令循环的大小超过在用于存储获取的指令的获取单元中分配的存储空间的大小; （ii）从提取单元请求获取遵循指令循环的第一指令的指令循环的指令; 以及（iii）在所述指令循环的迭代期间选择是否向所述调度单元提供所述指令循环的所述第一指令之一或由所述提取单元获取的另一指令; 其中指令循环的第一指令被存储在调度单元中。

公开(公告)号：US09606802B2

公开(公告)日：2017-03-28

申请号：US14006034

申请日：2011-03-25

申请人： Yuval Peled ,  Itzhak Barak ,  Uri Dayan ,  Amir Kleen ,  Idan Rozenberg

发明人： Yuval Peled ,  Itzhak Barak ,  Uri Dayan ,  Amir Kleen ,  Idan Rozenberg

IPC分类号： G06F9/44 ,  G06F9/315 ,  G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30116 ,  G06F9/3013

摘要： A processor system is adapted to carry out a predicate swap instruction of an instruction set to swap, via a data pathway, predicate data in a first predicate data location of a predicate register with data in a corresponding additional predicate data location of a first additional predicate data container and to swap, via a data pathway, predicate data in a second predicate storage location of the predicate register with data in a corresponding additional predicate data location in a second additional predicate data container.

公开(公告)号：US20140013087A1

公开(公告)日：2014-01-09

申请号：US14006034

申请日：2011-03-25

申请人： Yuval Peled ,  Itzhak Barak ,  Uri Dayan ,  Amir Kleen ,  Idan Rozenberg

发明人： Yuval Peled ,  Itzhak Barak ,  Uri Dayan ,  Amir Kleen ,  Idan Rozenberg

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30116 ,  G06F9/3013

摘要： A processor system is adapted to carry out a predicate swap instruction of an instruction set to swap, via a data pathway, predicate data in a first predicate data location of a predicate register with data in a corresponding additional predicate data location of a first additional predicate data container and to swap, via a data pathway, predicate data in a second predicate storage location of the predicate register with data in a corresponding additional predicate data location in a second additional predicate data container.

摘要翻译： 处理器系统适于执行指令集的谓词交换指令，以通过数据路径交换谓词寄存器的第一谓词数据位置中的数据，其中所述数据位于第一附加谓词的对应附加谓词数据位置中 数据容器，并且通过数据路径交换在谓词寄存器的第二谓词存储位置中的数据与第二附加谓词数据容器中的对应附加谓词数据位置中的数据。

公开(公告)号：US20100049954A1

公开(公告)日：2010-02-25

申请号：US12194279

申请日：2008-08-19

申请人： Guy Shmueli ,  Itzhak Barak ,  Uri Dayan ,  Amir Paran ,  Idan Rozenberg ,  Doron Schupper

发明人： Guy Shmueli ,  Itzhak Barak ,  Uri Dayan ,  Amir Paran ,  Idan Rozenberg ,  Doron Schupper

IPC分类号： G06F9/22

CPC分类号： G06F9/3842 ,  G06F9/30094

摘要： A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.

摘要翻译： 一种用于推测执行指令的方法，所述方法包括：对比较指令进行解码; 以连续的方式推测性地执行由与比较指令的分辨率相关的条件调节的条件指令，并且在比较指令的解码开始的推测窗口期间被解码，并且当比较指令被解析时结束 ; 并且停止依赖于至少一个条件指令的结果的非条件指令的执行，直到投机窗口结束为止。

公开(公告)号：US07930522B2

公开(公告)日：2011-04-19

申请号：US12194279

申请日：2008-08-19

申请人： Guy Shumeli ,  Itzhak Barak ,  Uri Dayan ,  Amir Paran ,  Idan Rozenberg ,  Doron Schupper

发明人： Guy Shumeli ,  Itzhak Barak ,  Uri Dayan ,  Amir Paran ,  Idan Rozenberg ,  Doron Schupper

IPC分类号： G06F9/48

CPC分类号： G06F9/3842 ,  G06F9/30094

摘要： A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.

摘要翻译： 一种用于推测执行指令的方法，所述方法包括：对比较指令进行解码; 以连续的方式推测性地执行由与比较指令的分辨率相关的条件调节的条件指令，并且在比较指令的解码开始的推测窗口期间被解码并且当比较指令被解析时结束 ; 并且停止依赖于至少一个条件指令的结果的非条件指令的执行，直到投机窗口结束为止。

公开(公告)号：US20100042811A1

公开(公告)日：2010-02-18

申请号：US12190291

申请日：2008-08-12

申请人： Yuval Peled ,  Itzhak Barak ,  Uri Dayan ,  Idan Rozenberg ,  Yoram Salant

发明人： Yuval Peled ,  Itzhak Barak ,  Uri Dayan ,  Idan Rozenberg ,  Yoram Salant

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/30094 ,  G06F9/3804 ,  G06F9/3844

摘要： A method for managing branch instructions, the method includes: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instruction during a single execution cycle; receiving, at a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages, each pipeline stage that generates an instruction fetch request stores a variable length group of instructions that comprises a branch instruction; sending to the fetch unit an instruction fetch command that is responsive to a first in order branch instruction in the pipeline stages; wherein if the first in order fetch command is a conditional fetch command then the instruction fetch command comprises a resolved target address; wherein the sending of the instruction fetch command is restricted to a single instruction fetch command per a single execution cycle.

摘要翻译： 一种用于管理分支指令的方法，所述方法包括：向处理器的流水线阶段提供多个可变长度的指令组; 其中每个流水线阶段在单个执行周期期间执行一组指令; 在某个执行周期接收来自多个流水线级的多个指令获取请求，生成指令提取请求的每个流水线级存储包括分支指令的可变长度的指令组; 向提取单元发送响应于流水线级中的第一顺序分支指令的指令获取命令; 其中如果所述第一顺序获取命令是条件获取命令，则所述指令获取命令包括解析的目标地址; 其中指令获取命令的发送被限制在单个执行周期中的单个指令获取命令。

公开(公告)号：US09672042B2

公开(公告)日：2017-06-06

申请号：US14396146

申请日：2012-05-29

申请人： Roy Glasner ,  Itzhak Barak ,  Yuval Peled ,  Idan Rozenberg ,  Lev Vaskevich

发明人： Roy Glasner ,  Itzhak Barak ,  Yuval Peled ,  Idan Rozenberg ,  Lev Vaskevich

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30196 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3853

摘要： A processing system comprises a processing device; a first instruction set encoded in a first encoding space and comprising one or more first instructions; a second instruction set encoded in a second encoding space different from the first encoding space and comprising two or more orthogonal second instructions; and an instruction encoder arranged to encode and encapsulate subsets of the second instructions in instruction containers, each instruction container sized to comprise a plurality of the second instructions.