公开(公告)号：US20070096333A1

公开(公告)日：2007-05-03

申请号：US11263412

申请日：2005-10-31

申请人： Amir Motamedi ,  Hermann Ruckerbauer

发明人： Amir Motamedi ,  Hermann Ruckerbauer

IPC分类号： H01L23/52

CPC分类号： H01L25/0652 ,  H01L23/36 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/05599

摘要： A multi-chip package and method is disclosed. In one embodiment, the multi-chip package includes at least four of spaced semiconductor integrated circuit chips mounted on a printed circuit board, consisting of the first pair of the semiconductor integrated circuit chips and the second pair of the semiconductor integrated circuit chips. The chips of the first pair of the semiconductor integrated circuit chips are arranged substantially parallel and the chips of the semiconductor integrated circuit chips of the second pair are arranged substantially stacked over the chips of the first pair of the semiconductor integrated circuit chips.

摘要翻译： 公开了一种多芯片封装和方法。 在一个实施例中，多芯片封装包括安装在由第一对半导体集成电路芯片和第二对半导体集成电路芯片组成的印刷电路板上的间隔开的半导体集成电路芯片中的至少四个。 第一对半导体集成电路芯片的芯片基本上平行布置，并且第二对的半导体集成电路芯片的芯片基本上堆叠在第一对半导体集成电路芯片的芯片上。

公开(公告)号：US07342815B2

公开(公告)日：2008-03-11

申请号：US11214067

申请日：2005-08-30

申请人： Hermann Ruckerbauer ,  Georg Braun ,  Amir Motamedi

发明人： Hermann Ruckerbauer ,  Georg Braun ,  Amir Motamedi

IPC分类号： G11C5/06

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096

摘要： A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on and turned off, and the chip end of the data line is connected to a positive or to a less positive, grounded, or negative supply voltage line by a pull-up or pull-down resistor. Alternatively, a data transmission system is operated with a timing by which the termination circuits to be turned on for respective operating state are not turned on until the drivers to be activated for the respective operating state have been activated.

摘要翻译： 特别是作为DDR-III存储器芯片通信电路的一部分的数据传输系统执行无前导码的数据传输操作。 该数据传输系统包括至少一条具有可接通和关断的管芯端接的数据线，并且数据线的芯片端连接到正极或接地或负极的电源电压线 通过上拉或下拉电阻。 或者，数据传输系统的操作是在相应的运行状态下接通的终端电路不被打开的定时，直到被激活的驱动程序被激活为止。

公开(公告)号：US20070109903A1

公开(公告)日：2007-05-17

申请号：US11272023

申请日：2005-11-14

申请人： Amir Motamedi

发明人： Amir Motamedi

IPC分类号： G11C8/00

CPC分类号： G06F17/5036

摘要： A method of developing the physical layout of an electronic component in a data bus connected logic analog system includes: providing a data bus connected logic analog system modeled as a software-implemented channel simulation model including: a bit pattern generator for generating a bit pattern; the electronic component, whose physical layout is to be determined by being modeled as a black box characterized by model parameters; and a bit pattern analyzer for analyzing a bit error rate of the bit pattern; sending an input bit pattern through the black box to produce an output bit pattern and comparing the output bit pattern with the input bit pattern to determine a bit error rate; and varying the model parameters and repeating the process until the determined bit error rate is below a pre-determined value to determine at least one critical model parameter boundary.

公开(公告)号：US07293250B2

公开(公告)日：2007-11-06

申请号：US11272023

申请日：2005-11-14

申请人： Amir Motamedi

发明人： Amir Motamedi

IPC分类号： G06F17/50 ,  G06G7/48

CPC分类号： G06F17/5036

摘要： A method of developing the physical layout of an electronic component in a data bus connected logic analog system includes: providing a data bus connected logic analog system modeled as a software-implemented channel simulation model including: a bit pattern generator for generating a bit pattern; the electronic component, whose physical layout is to be determined by being modeled as a black box characterized by model parameters; and a bit pattern analyzer for analyzing a bit error rate of the bit pattern; sending an input bit pattern through the black box to produce an output bit pattern and comparing the output bit pattern with the input bit pattern to determine a bit error rate; and varying the model parameters and repeating the process until the determined bit error rate is below a pre-determined value to determine at least one critical model parameter boundary.

摘要翻译： 一种在数据总线连接逻辑模拟系统中开发电子部件的物理布局的方法包括：提供建模为软件实现的信道模拟模型的数据总线连接逻辑模拟系统，包括：位模式发生器，用于产生位模式; 该电子部件的物理布局将通过模型化为以模型参数为特征的黑盒来确定; 以及用于分析比特模式的比特错误率的比特模式分析器; 通过黑盒发送输入位模式以产生输出位模式并将输出位模式与输入位模式进行比较以确定误码率; 并改变模型参数并重复该过程，直到所确定的误码率低于预定值以确定至少一个关键模型参数边界。

公开(公告)号：US20060062039A1

公开(公告)日：2006-03-23

申请号：US11214067

申请日：2005-08-30

申请人： Hermann Ruckerbauer ,  Georg Braun ,  Amir Motamedi

发明人： Hermann Ruckerbauer ,  Georg Braun ,  Amir Motamedi

IPC分类号： G11C5/06

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096

摘要： A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on and turned off, and the chip end of the data line is connected to a positive or to a less positive, grounded, or negative supply voltage line by a pull-up or pull-down resistor. Alternatively, a data transmission system is operated with a timing by which the termination circuits to be turned on for respective operating state are not turned on until the drivers to be activated for the respective operating state have been activated.

摘要翻译： 特别是作为DDR-III存储器芯片通信电路的一部分的数据传输系统执行无前导码的数据传输操作。 该数据传输系统包括至少一条具有可接通和关断的管芯端接的数据线，并且数据线的芯片端连接到正极或接地或负极的电源电压线 通过上拉或下拉电阻。 或者，数据传输系统的操作是在相应的运行状态下接通的终端电路不被打开的定时，直到被激活的驱动程序被激活为止。