DQS signaling in DDR-III memory systems without preamble
    1.
    发明申请
    DQS signaling in DDR-III memory systems without preamble 有权
    没有前导码的DDR-III存储器系统中的DQS信号

    公开(公告)号:US20060062039A1

    公开(公告)日:2006-03-23

    申请号:US11214067

    申请日:2005-08-30

    IPC分类号: G11C5/06

    摘要: A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on and turned off, and the chip end of the data line is connected to a positive or to a less positive, grounded, or negative supply voltage line by a pull-up or pull-down resistor. Alternatively, a data transmission system is operated with a timing by which the termination circuits to be turned on for respective operating state are not turned on until the drivers to be activated for the respective operating state have been activated.

    摘要翻译: 特别是作为DDR-III存储器芯片通信电路的一部分的数据传输系统执行无前导码的数据传输操作。 该数据传输系统包括至少一条具有可接通和关断的管芯端接的数据线,并且数据线的芯片端连接到正极或接地或负极的电源电压线 通过上拉或下拉电阻。 或者,数据传输系统的操作是在相应的运行状态下接通的终端电路不被打开的定时,直到被激活的驱动程序被激活为止。

    Optimal stacked die organization
    2.
    发明申请
    Optimal stacked die organization 审中-公开
    最佳堆叠模组织

    公开(公告)号:US20070096333A1

    公开(公告)日:2007-05-03

    申请号:US11263412

    申请日:2005-10-31

    IPC分类号: H01L23/52

    摘要: A multi-chip package and method is disclosed. In one embodiment, the multi-chip package includes at least four of spaced semiconductor integrated circuit chips mounted on a printed circuit board, consisting of the first pair of the semiconductor integrated circuit chips and the second pair of the semiconductor integrated circuit chips. The chips of the first pair of the semiconductor integrated circuit chips are arranged substantially parallel and the chips of the semiconductor integrated circuit chips of the second pair are arranged substantially stacked over the chips of the first pair of the semiconductor integrated circuit chips.

    摘要翻译: 公开了一种多芯片封装和方法。 在一个实施例中,多芯片封装包括安装在由第一对半导体集成电路芯片和第二对半导体集成电路芯片组成的印刷电路板上的间隔开的半导体集成电路芯片中的至少四个。 第一对半导体集成电路芯片的芯片基本上平行布置,并且第二对的半导体集成电路芯片的芯片基本上堆叠在第一对半导体集成电路芯片的芯片上。

    DQS signaling in DDR-III memory systems without preamble
    3.
    发明授权
    DQS signaling in DDR-III memory systems without preamble 有权
    没有前导码的DDR-III存储器系统中的DQS信号

    公开(公告)号:US07342815B2

    公开(公告)日:2008-03-11

    申请号:US11214067

    申请日:2005-08-30

    IPC分类号: G11C5/06

    摘要: A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on and turned off, and the chip end of the data line is connected to a positive or to a less positive, grounded, or negative supply voltage line by a pull-up or pull-down resistor. Alternatively, a data transmission system is operated with a timing by which the termination circuits to be turned on for respective operating state are not turned on until the drivers to be activated for the respective operating state have been activated.

    摘要翻译: 特别是作为DDR-III存储器芯片通信电路的一部分的数据传输系统执行无前导码的数据传输操作。 该数据传输系统包括至少一条具有可接通和关断的管芯端接的数据线,并且数据线的芯片端连接到正极或接地或负极的电源电压线 通过上拉或下拉电阻。 或者,数据传输系统的操作是在相应的运行状态下接通的终端电路不被打开的定时,直到被激活的驱动程序被激活为止。

    Memory system and method for transferring data therein
    4.
    发明授权
    Memory system and method for transferring data therein 有权
    用于在其中传输数据的存储器系统和方法

    公开(公告)号:US07831797B2

    公开(公告)日:2010-11-09

    申请号:US11862915

    申请日:2007-09-27

    IPC分类号: G06F12/00

    CPC分类号: G11C7/1018 G06F13/1684

    摘要: A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from a first and second set of memory chips. Transfer of an internal packet data from the control device to memory takes place such that a first record is stored in a second set of memory chips and additional records are stored in the first set of memory chips. In preferred embodiments, data is allocated in the second set of memory chips such that at least one additional transfer step takes place to the second set of memory chips compared with transfers to the first set of memory chips. In the additional transfer step(s), the first set of memory chips is masked from receiving data.

    摘要翻译: 存储器系统在功能上被设计成使得尽管在没有纠错装置的情况下进行操作,但实际提供用于纠错的存储器模块的存储器芯片被同时用于数据传输。 控制装置被配置为接收,存储和传送数据分组到第一和第二组存储器芯片。 将内部分组数据从控制设备传送到存储器进行,使得第一记录被存储在第二组存储器芯片中,并且附加记录被存储在第一组存储器芯片中。 在优选实施例中,在第二组存储器芯片中分配数据,使得与传送到第一组存储器芯片相比,至少一个额外的转移步骤发生到第二组存储器芯片。 在附加传送步骤中,第一组存储器芯片被从接收数据中被掩蔽。

    Method of refreshing data in a storage location based on heat dissipation level and system thereof
    5.
    发明授权
    Method of refreshing data in a storage location based on heat dissipation level and system thereof 有权
    基于散热水平及其系统刷新存储位置中的数据的方法

    公开(公告)号:US07768857B2

    公开(公告)日:2010-08-03

    申请号:US11949639

    申请日:2007-12-03

    IPC分类号: G11C7/04

    摘要: An integrated device comprising a storage location, wherein data stored in the storage location is repeatedly refreshed with a first predetermined refresh rate during a first period of time. The first period of time provides a first predetermined duration. After the end of the first period of time, the data is repeatedly refreshed with a second predetermined refresh rate.

    摘要翻译: 一种包括存储位置的集成设备,其中存储在所述存储位置中的数据在第一时间段期间以第一预定刷新率重复地刷新。 第一时间段提供第一预定持续时间。 在第一时间段结束之后,数据以第二预定刷新率反复刷新。

    MULTI MASTER DRAM ARCHITECTURE
    6.
    发明申请
    MULTI MASTER DRAM ARCHITECTURE 有权
    多主体DRAM架构

    公开(公告)号:US20100077157A1

    公开(公告)日:2010-03-25

    申请号:US12235063

    申请日:2008-09-22

    IPC分类号: G06F12/00 G06F13/14

    摘要: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, the memory device may be a package comprising a plurality of stacked memory dies.

    摘要翻译: 本发明的实施例提供一种存储器件,其可以经由存储器件的相应端口被多个控制器或处理器核存取。 每个控制器可以经由数据总线耦合到存储器设备的相应端口。 存储器设备的每个端口可以与存储器的预定义部分相关联,从而使每个控制器访问不同部分的存储器,而不受其他控制器的干扰。 公共命令/地址总线可以将多个控制器耦合到存储器设备。 每个控制器可以在存储器访问控制总线上断言有效信号以获得对命令/地址总线的访问以启动存储器访问。 在一些实施例中,存储器件可以是包括多个堆叠的存储器管芯的封装。