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    METHOD AND APPARATUS FOR ANALOG TO DIGITAL ERROR CONVERSION WITH MULTIPLE SYMMETRIC TRANSFER FUNCTIONS
    2.
    发明申请
    METHOD AND APPARATUS FOR ANALOG TO DIGITAL ERROR CONVERSION WITH MULTIPLE SYMMETRIC TRANSFER FUNCTIONS 审中-公开

    公开(公告)号：US20180262202A1

    公开(公告)日：2018-09-13

    申请号：US15977826

    申请日：2018-05-11

    申请人： AnDAPT, Inc.

    发明人： Maheen SAMAD ,  Patrick J. CROTTY ,  John BIRKNER ,  Herman CHEUNG ,  Kapil SHANKAR

    IPC分类号： H03M1/10 ,  H03K19/0175 ,  H03K19/00

    CPC分类号： H03M1/1014 ,  H03K19/0008 ,  H03K19/017581 ,  H03M1/08 ,  H03M1/60

    摘要： An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals. Each of the two counters receives a respective pulse signal from the VCO and generate a digital counter value. The error generator block receives digital counter values from the two digital counters generates a digital conversion code corresponding to a difference between the digital counter values.

    NOISE-IMMUNE REFERENCE (NREF) INTEGRATED IN A PROGRAMMABLE LOGIC DEVICE
    4.
    发明申请
    NOISE-IMMUNE REFERENCE (NREF) INTEGRATED IN A PROGRAMMABLE LOGIC DEVICE 审中-公开

    公开(公告)号：US20180205381A1

    公开(公告)日：2018-07-19

    申请号：US15921201

    申请日：2018-03-14

    申请人： AnDAPT, Inc.

    发明人： Patrick J. CROTTY ,  John BIRKNER ,  Kapil SHANKAR

    IPC分类号： H03K19/177 ,  H03G3/20

    CPC分类号： H03K19/17764 ,  H03G1/0088 ,  H03G3/20 ,  H03K19/17728 ,  H03K19/17744

    摘要： A reference voltage block integrated in a programmable logic device (PLD) includes: an accumulator comprising an adder and a register and configured to receive a digital reference value and generate a carry out signal; a low-pass filter configured to receive the carry out signal from the accumulator and generate a filtered signal; and a variable analog gain amplifier configured to amplify the filtered signal using a gain selected from a predetermined set of gains and generate a reference voltage output signal. The PLD includes a programmable fabric and a signal wrapper that is configured to provide signals between the reference voltage block and the programmable fabric. The digital reference value and the predetermined set of gains of the reference voltage block are programmably using the programmable fabric and fed to the reference voltage block via the signal wrapper.

    NOISE-IMMUNIE REFERENCE (NREF) INTERGARED IN A PROGRAMMABLE LOGIC DEVICE
    6.
    发明申请
    NOISE-IMMUNIE REFERENCE (NREF) INTERGARED IN A PROGRAMMABLE LOGIC DEVICE 有权

    公开(公告)号：US20180026643A1

    公开(公告)日：2018-01-25

    申请号：US15656982

    申请日：2017-07-21

    申请人： AnDAPT, Inc.

    发明人： Patrick J. CROTTY ,  John BIRKNER ,  Kapil SHANKAR

    IPC分类号： H03K19/177 ,  H03G3/20

    CPC分类号： H03K19/17764 ,  H03G1/0088 ,  H03G3/20 ,  H03K19/17728 ,  H03K19/17744

    摘要： A reference voltage block integrated in a programmable logic device (PLD) includes: an accumulator comprising an adder and a register and configured to receive a digital reference value and generate a carry out signal; a low-pass filter configured to receive the carry out signal from the accumulator and generate a filtered signal; and a variable analog gain amplifier configured to amplify the filtered signal using a gain selected from a predetermined set of gains and generate a reference voltage output signal. The PLD includes a programmable fabric and a signal wrapper that is configured to provide signals between the reference voltage block and the programmable fabric. The digital reference value and the predetermined set of gains of the reference voltage block are programmably using the programmable fabric and fed to the reference voltage block via the signal wrapper.

    PROGRAMMABLE ANALOG AND DIGITAL INPUT/OUTPUT FOR POWER APPLICATION
    7.
    发明申请
    PROGRAMMABLE ANALOG AND DIGITAL INPUT/OUTPUT FOR POWER APPLICATION 有权

    公开(公告)号：US20180026636A1

    公开(公告)日：2018-01-25

    申请号：US15656965

    申请日：2017-07-21

    申请人： AnDAPT, Inc.

    发明人： John BIRKNER ,  Kapil SHANKAR ,  Herman CHEUNG ,  Patrick J. CROTTY ,  Ranajit GHOMAN

    IPC分类号： H03K19/0175 ,  H03K5/24

    CPC分类号： H03K19/017581 ,  H02M3/1588 ,  H03K5/24 ,  H03K17/162 ,  H03K19/0016 ,  H03K19/017509 ,  H03K19/177

    摘要： A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals; an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD; a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; and I/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric. The threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programmable fabric and the signal wrapper.