公开(公告)号：US09270292B2

公开(公告)日：2016-02-23

申请号：US14769945

申请日：2014-03-07

Applicant: Anacatum Design AB

Inventor： Rolf Sundblad ,  Emil Hjalmarsson

IPC: H03M1/00 ,  H03M1/12

CPC classification number: H03M1/1255 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/126

Abstract: A time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises an array of N constituent analog-to-digital converters that operate based on an analog-to-digital converter operation clock to provide the digital output signal, N sample-and-hold units connected to the input of a respective constituent analog-to-digital converter that operate based on a respective one of M of timing signals, wherein no timing signal is used to clock two or more of the sample-and-hold units, one or more digital output processing units that provide a sample of the digital output of a constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals, and a timing circuit that generates the analog-to-digital converter operation clock signal, each timing signal having a period of M/R, wherein M is less or equal to N.

Abstract translation: 用于将模拟输入信号转换为具有采样率R的数字输出信号的时间交织的模拟 - 数字转换器包括基于模数转换器操作的N个组成模数转换器的阵列 操作时钟以提供数字输出信号，N个采样保持单元连接到基于M个定时信号中的相应一个的相应组成模数转换器的输入，其中不使用定时信号 时钟两个或更多个采样和保持单元，一个或多个数字输出处理单元，其基于相应的一个提供组成模数转换器的数字输出的采样作为数字输出信号的采样 的M个定时信号，以及定时电路，其生成模数转换器操作时钟信号，每个定时信号具有M / R周期，其中M小于或等于N.

公开(公告)号：US09602123B2

公开(公告)日：2017-03-21

申请号：US15107568

申请日：2014-12-03

Applicant: Anacatum Design AB ,  Fingerprint Cards AB

Inventor： Rolf Sundblad ,  Staffan Holmbring ,  Robert Hägglund ,  Emil Hjalmarsson

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/10 ,  H03M1/38 ,  H03M1/46 ,  H03M1/06

CPC classification number: H03M1/1245 ,  H03M1/0624 ,  H03M1/1009 ,  H03M1/1265 ,  H03M1/38 ,  H03M1/46

Abstract: A cognitive signal converter adapted to produce a digital output signal based on an analog input signal comprises an analog-to-digital converter (ADC) and a cognitive network. The ADC is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and quantizing each analog input signal sample based on the process clock signal. The cognitive network is adapted to receive the digital converted signal of the ADC, control at least one of the sample clock signal and the process clock signal based on the received digital converted signal and one or more characteristics of the analog signal source, and produce the digital output signal based on the received digital converted signal. Corresponding integrated circuit, electronic device and method are also disclosed.