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公开(公告)号：US10038452B2
公开(公告)日：2018-07-31
申请号：US15649313
申请日：2017-07-13
Applicant: Analog Devices, Inc.
Inventor： Baozhen Chen , Edward C. Guthrie , Michael C. W. Coln , Mark D. Maddox
CPC classification number: H03M1/0836 , H03M1/0651 , H03M1/0863 , H03M1/14 , H03M1/466 , H03M1/68 , H03M1/804 , H03M1/806
Abstract: During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.
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公开(公告)号：US09712181B1
公开(公告)日：2017-07-18
申请号：US15273967
申请日：2016-09-23
Applicant: Analog Devices, Inc.
Inventor： Baozhen Chen , Edward C. Guthrie , Michael C. W. Coln , Mark D. Maddox
CPC classification number: H03M1/466 , H03M1/0863 , H03M1/1245 , H03M1/14 , H03M1/68 , H03M1/804 , H03M1/806
Abstract: During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.
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公开(公告)号：US09571114B1
公开(公告)日：2017-02-14
申请号：US15019430
申请日：2016-02-09
Applicant: Analog Devices, Inc.
Inventor： Junhua Shen , Edward C. Guthrie
CPC classification number: H03M1/0612 , H03M1/069 , H03M1/1245 , H03M1/46
Abstract: An analog-to-digital converter (ADC) circuit comprises a digital-to-analog (DAC) circuit including at least N+n weighted circuit components, wherein N and n are positive integers greater than zero, and n is a number of repeat bits of the least significant bit (LSB) of the ADC circuit; a sampling circuit configured to sample an input voltage at an input to the ADC circuit and apply a sampled voltage to the weighted circuit components; a comparator circuit configured to compare an output voltage of the DAC to a specified threshold voltage during a bit trial; and logic circuitry configured to perform bit trials for the at least N+n weighted circuit components and adjust one or more parameters for one or more of N bit trials according to values of the n LSB repeat bits.
Abstract translation: 模数转换器（ADC）电路包括至少包括N + n个加权电路组件的数模（DAC）电路，其中N和n是大于零的正整数，n是重复数 ADC电路的最低有效位（LSB）的位; 采样电路，被配置为在所述ADC电路的输入处对输入电压进行采样，并将采样的电压施加到所述加权电路部件; 比较器电路，被配置为在比特试验期间将DAC的输出电压与指定的阈值电压进行比较; 以及逻辑电路，被配置为对所述至少N + n个加权电路组件执行比特测试，并根据n个LSB重复比特的值调整一个或多个N比特试验中的一个或多个参数。
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公开(公告)号：US20180091165A1
公开(公告)日：2018-03-29
申请号：US15649313
申请日：2017-07-13
Applicant: Analog Devices, Inc.
Inventor： Baozhen Chen , Edward C. Guthrie , Michael C.W. Coln , Mark D. Maddox
IPC: H03M1/08
CPC classification number: H03M1/0836 , H03M1/0651 , H03M1/0863 , H03M1/14 , H03M1/466 , H03M1/68 , H03M1/804 , H03M1/806
Abstract: During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.
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