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    RESISTIVE THERMOMETER EXCITATION AND CALIBRATION
    1.
    发明申请
    RESISTIVE THERMOMETER EXCITATION AND CALIBRATION 有权

    公开(公告)号：US20250137853A1

    公开(公告)日：2025-05-01

    申请号：US18499514

    申请日：2023-11-01

    Applicant: Analog Devices, Inc.

    Inventor： Michael C.W. Coln ,  Phillip Michel Nadeau ,  Qingdong Meng

    IPC: G01K7/20 ,  G01K1/02 ,  G01K7/18

    Abstract: Circuitry and measurement approaches are described herein that can be used to reduce or suppress sensitivity to variation of sensor properties or characteristics over time for a respective monolithically integrated resistive temperature sensor. Such measurement approaches can also help to suppress measurement variations between sensors, such as to provide stable temperature measurement characteristics across locations and over time for the respective different temperature measurement sites on or within the integrated circuit package. The approaches described herein can also reduce or suppress sensitivity to variation in excitation source characteristics, such as using a relative indication (e.g., a ratio) of measured signal values corresponding to a respective temperature sensor and a co-integrated reference device. Calibration or absolute temperature measurements can be performed, such as using an off-chip (e.g., off-die or off-package) calibration reference. The off-chip calibration reference can be used to establish calibration data for other measurements.

    CORRELATED DOUBLE SAMPLING AMPLIFIER FOR LOW POWER
    2.
    发明申请
    CORRELATED DOUBLE SAMPLING AMPLIFIER FOR LOW POWER 审中-公开

    公开(公告)号：US20200057484A1

    公开(公告)日：2020-02-20

    申请号：US16103963

    申请日：2018-08-16

    Applicant: Analog Devices, Inc.

    Inventor： Michael C.W. Coln ,  Michael Mueck

    IPC: G06F1/32 ,  H03F3/45 ,  H03M1/38 ,  H03M1/12

    Abstract: A signal acquisition or conditioning amplifier can be configured and controlled to use correlated doubling sampling (CDS) of a differential input signal, and a storage capacitor in a capacitive or other feedback network, a low power operational transconductance amplifier (OTA) capable of being powered down between CDS samplings, and which can be operated in a manner that provides good performance characteristics while still providing low or efficient power consumption. The amplifier and other signal processing circuitry can allow power to be scaled down, when less signal measurement throughput is needed, and to be scaled up, when more signal measurement throughput is needed. Such flexibility can help make the present approach useful for a wide range of signal acquisition and measurement applications. Precharging via buffer amplifiers can provide improved signal acquisition circuitry effective input impedance.

    COMMON MODE REJECTION IN A RESERVOIR CAPACITOR SAR CONVERTER
    5.
    发明申请
    COMMON MODE REJECTION IN A RESERVOIR CAPACITOR SAR CONVERTER 审中-公开

    公开(公告)号：US20180019761A1

    公开(公告)日：2018-01-18

    申请号：US15213078

    申请日：2016-07-18

    Applicant: Analog Devices, Inc.

    Inventor： Michael C.W. Coln

    IPC: H03M1/12 ,  H03M1/46

    CPC classification number: H03M1/1245 ,  H03M1/0607 ,  H03M1/466

    Abstract: An analog-to-digital converter (ADC) circuit comprises a first digital-to-analog (DAC) circuit and a second DAC circuit, wherein the first and second DAC circuits include weighted bit capacitors and reservoir capacitors; a sampling circuit configured to sample a differential input voltage onto the weighted bit capacitors and to sample a reference voltage onto the reservoir capacitors; a comparator circuit operatively coupled to outputs of the first and DAC circuits; and logic circuitry configured to: initiate successive bit trials of weighted bit capacitors to convert the input voltage to a digital value by comparing an output of the first DAC circuit and an output of second DAC circuit using the comparator circuit; and apply charge of the reservoir capacitors to the bit capacitors to reduce the comparator differential input voltage and reduce an error between the input common mode offset and the comparator common mode offset.

    ENHANCED AUTO-ZERO CIRCUIT
    6.
    发明申请
    ENHANCED AUTO-ZERO CIRCUIT 有权

    公开(公告)号：US20240396510A1

    公开(公告)日：2024-11-28

    申请号：US18202241

    申请日：2023-05-25

    Applicant: Analog Devices, Inc.

    Inventor： Michael C.W. Coln ,  Qingdong Meng ,  Phillip Michel Nadeau

    IPC: H03F3/45

    Abstract: An enhanced auto-zero circuitry and technique for reducing the effective input offset voltage of an amplifier. The circuitry includes a multi-phase auto-zeroing amplifier circuitry including several capacitor and switch components and a switch controller circuit. The switch controller circuit is configured to provide control signals for controlling the switches, where during a first sub-phase of an auto-zero phase, multiple switches are turned on to store an amplifier input offset coarser compensation charge on the input capacitor, and where during a second sub-phase of the auto-zero phase, at least one switch is turned off before turning on another switch to store an amplifier input offset finer compensation charge on the input capacitor via the first auto-zero capacitor.

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