中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.014 seconds)

    SAR ADCs with dedicated reference capacitor for each bit capacitor
    2.
    发明授权
    SAR ADCs with dedicated reference capacitor for each bit capacitor 有权

    公开(公告)号：US10205462B2

    公开(公告)日：2019-02-12

    申请号：US14949423

    申请日：2015-11-23

    Applicant: ANALOG DEVICES, INC.

    Inventor： Junhua Shen ,  Mark D. Maddox ,  Ronald Alan Kapusta

    IPC: H03M1/12 ,  H03M1/46 ,  H03M1/08 ,  H03M1/00

    Abstract: A successive approximation register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal independent (can be easily measured and corrected/calibrated).

    SAR ADCS WITH DEDICATED REFERENCE CAPACITOR FOR EACH BIT CAPACITOR
    4.
    发明申请
    SAR ADCS WITH DEDICATED REFERENCE CAPACITOR FOR EACH BIT CAPACITOR 审中-公开
    具有专用参考电容器的SAR ADCS，用于每个位电容器

    公开(公告)号：US20160182078A1

    公开(公告)日：2016-06-23

    申请号：US14949423

    申请日：2015-11-23

    Applicant: ANALOG DEVICES, INC.

    Inventor： JUNHUA SHEN ,  Mark D. Maddox ,  Ronald Alan Kapusta

    IPC: H03M1/46 ,  H03M1/00

    CPC classification number: H03M1/468 ,  H03M1/002 ,  H03M1/08 ,  H03M1/462

    Abstract: A successive approximation register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal independent (can be easily measured and corrected/calibrated).

    Abstract translation: 逐次逼近寄存器模拟 - 数字转换器（SAR ADC）通常包括用于实现将模拟输入逐位转换为数字输出的位测试的电路。 用于比特测试的电路通常是加权（例如，二进制加权），并且这些比特权重并不总是理想的。 校准算法可校准或校正非理想比特权重，并且通常将这些比特权重优先于信号无关，以便可以容易地测量和校准/校正比特权重。 本文公开的实施例涉及SAR ADC的独特电​​路设计，其中每个位电容器或一对位电容器（在差分设计中）具有相应的专用片上参考电容器。 由于片上参考电容（提供快速参考建立时间），所得ADC的速度很快，而与SAR ADC的非理想位权重有关的错误与信号无关（可以轻松测量和校正/校准） 。

    SAR ADCS WITH DEDICATED REFERENCE CAPACITOR FOR EACH BIT CAPACITOR
    5.
    发明申请
    SAR ADCS WITH DEDICATED REFERENCE CAPACITOR FOR EACH BIT CAPACITOR 审中-公开

    公开(公告)号：US20190123760A1

    公开(公告)日：2019-04-25

    申请号：US16228392

    申请日：2018-12-20

    Applicant: Analog Devices, Inc.

    Inventor： Junhua SHEN ,  Mark D. Maddox ,  Ronald Alan KAPUSTA

    IPC: H03M1/46 ,  H03M1/08

    Abstract: A successive-approximation-register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal-independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal-independent (can be easily measured and corrected/calibrated).

    CALIBRATION TECHNIQUES FOR SAR ADCS WITH ON-CHIP RESERVOIR CAPACITORS
    7.
    发明申请
    CALIBRATION TECHNIQUES FOR SAR ADCS WITH ON-CHIP RESERVOIR CAPACITORS 有权
    具有片上储存电容器的SAR ADCS校准技术

    公开(公告)号：US20160182077A1

    公开(公告)日：2016-06-23

    申请号：US14747071

    申请日：2015-06-23

    Applicant: ANALOG DEVICES, INC.

    Inventor： Mark D. Maddox ,  MICHAEL COLN ,  GARY R. CARREAU ,  BAOZHEN CHEN

    IPC: H03M1/10 ,  H03M1/40

    CPC classification number: H03M1/1071 ,  H03M1/1038 ,  H03M1/462 ,  H03M1/468

    Abstract: When reservoir capacitors are moved on-chip for individual bit decisions, a successive approximation register analog-to-digital converter (SAR ADC) has an addition source of error which can significantly affect the performance of the SAR ADC. Calibration techniques can be applied to measure and correct for such error in an SAR ADC using decide-and-set switching. Specifically, a calibration technique can expose the effective bit weight of each bit under test using a plurality of special input voltages and storing a calibration word for each bit under test to correct for the error. Such a calibration technique can lessen the need to store a calibration word for each possible output word to correct the additional source of error. Furthermore, another calibration technique can expose the effective bit weight of each bit under test without having to generate the plurality of special input voltages.

    Abstract translation: 当存储器电容器在芯片上移动以进行单独的位决定时，逐次逼近寄存器模数转换器（SAR ADC）具有可能显着影响SAR ADC性能的加法误差源。 校准技术可以用于使用决定和设置切换来测量和校正SAR ADC中的这种误差。 具体来说，校准技术可以使用多个特殊输入电压来暴露所测试的每个位的有效位权重，并且存储用于每一位被测位的校准字以校正错误。 这种校准技术可以减少为每个可能的输出字存储校准字以校正附加的误差源的需要。 此外，另一种校准技术可以暴露每个被测位的有效位重量，而不必产生多个特殊输入电压。

    Calibration techniques for SAR ADCs with on-chip reservoir capacitors
    9.
    发明授权
    Calibration techniques for SAR ADCs with on-chip reservoir capacitors 有权

    公开(公告)号：US09641189B2

    公开(公告)日：2017-05-02

    申请号：US14747071

    申请日：2015-06-23

    Applicant: ANALOG DEVICES, INC.

    Inventor： Mark D. Maddox ,  Michael Coln ,  Gary R. Carreau ,  Baozhen Chen

    IPC: H03M1/12 ,  H03M1/10 ,  H03M1/46

    CPC classification number: H03M1/1071 ,  H03M1/1038 ,  H03M1/462 ,  H03M1/468

    Abstract: When reservoir capacitors are moved on-chip for individual bit decisions, a successive approximation register analog-to-digital converter (SAR ADC) has an addition source of error which can significantly affect the performance of the SAR ADC. Calibration techniques can be applied to measure and correct for such error in an SAR ADC using decide-and-set switching. Specifically, a calibration technique can expose the effective bit weight of each bit under test using a plurality of special input voltages and storing a calibration word for each bit under test to correct for the error. Such a calibration technique can lessen the need to store a calibration word for each possible output word to correct the additional source of error. Furthermore, another calibration technique can expose the effective bit weight of each bit under test without having to generate the plurality of special input voltages.

Patent Agency Ranking