公开(公告)号：US09513647B2

公开(公告)日：2016-12-06

申请号：US14673137

申请日：2015-03-30

Applicant: Analog Devices Global

Inventor： Ulrik Sørensen Wismar ,  Khiem Quang Nguyen

IPC: H03K17/04 ,  G05F1/575

CPC classification number: G05F1/575

Abstract: The present invention relates in one aspect to a DC linear voltage regulator circuit for generating a regulated DC output voltage based on a DC input voltage. The DC linear voltage regulator circuit comprises a DMOS pass transistor comprising drain, gate, source and bulk terminals wherein the drain terminal is connected to a regulator output which is configured to supply the regulated DC output voltage and the source terminal is connected to a regulator input for receipt of the DC input voltage. The DC linear voltage regulator circuit comprises a switchable leakage prevention circuit, connected to the bulk terminal of the DMOS pass transistor, and configured to automatically detect and interrupt a flow of leakage current from the regulator output to the bulk terminal.

Abstract translation: 本发明在一个方面涉及一种用于基于直流输入电压产生稳定的直流输出电压的直流线性稳压器电路。 DC线性稳压器电路包括DMOS传输晶体管，其包括漏极，栅极，源极和体积端子，其中漏极端子连接到调节器输出，该稳压器输出被配置为提供稳压的DC输出电压，并且源极端子连接到调节器输入 用于接收直流输入电压。 直流线性稳压器电路包括可切换的防漏电路，连接到DMOS传输晶体管的批量端子，并被配置为自动检测和中断从稳压器输出到散装端子的泄漏电流。

公开(公告)号：US09503120B1

公开(公告)日：2016-11-22

申请号：US15056315

申请日：2016-02-29

Applicant: Analog Devices Global

Inventor： Zhichao Tan ,  Khiem Quang Nguyen

IPC: H03M3/00

CPC classification number: H03M3/328 ,  H03M3/30 ,  H03M3/42 ,  H03M3/424

Abstract: A sigma-delta modulator circuit selectively removes a dither signal previously added to an input of a quantizer circuit from the quantizer circuit output when addition of the dither signal causes a digital state change in the quantizer circuit output. Various examples for enabling the selective removal of the dither signal are described. In one embodiment, a second quantizer circuit provides a non-dithered output signal for comparison, by a digital comparator, with the dithered output signal. In another embodiment, a single quantizer circuit provides the dithered and non-dithered output signals in turn, for comparison. A subtraction circuit may remove the dither signal as appropriate. Embodiments enable retention of the improved limit cycle tone reduction achievable via dithering while reducing the need for circuits with increased signal headroom, and associated design complexity and power dissipation.

Abstract translation: 当加入抖动信号导致量化器电路输出中的数字状态改变时，Σ-Δ调制器电路从量化器电路输出中选择性地去除先前添加到量化器电路的输入的抖动信号。 描述了能够选择性地去除抖动信号的各种示例。 在一个实施例中，第二量化器电路提供非抖动输出信号，用于通过数字比较器与抖动输出信号进行比较。 在另一个实施例中，单个量化器电路依次提供抖动和不抖动的输出信号，用于比较。 减法电路可以适当地去除抖动信号。 实施例使得能够保持通过抖动可实现的改进的限制循环音调降低，同时减少对具有增加的信号净空的电路的需要，以及相关的设计复杂性和功率耗散。

公开(公告)号：US09479865B2

公开(公告)日：2016-10-25

申请号：US14231192

申请日：2014-03-31

Applicant: Analog Devices Global

Inventor： Khiem Quang Nguyen ,  Kim Spetzler Berthelsen ,  Robert Adams

IPC: H04R3/00 ,  H03M3/00 ,  H03F3/181 ,  H03F3/38 ,  H03F1/32 ,  G06F3/043

CPC classification number: H04R3/00 ,  G06F3/0433 ,  H03F1/32 ,  H03F3/181 ,  H03F3/38 ,  H03F2200/03 ,  H03M3/356

Abstract: A transducer amplification circuit may include a preamplifier circuit with a signal input receiving a transducer signal to provide an amplified transducer signal comprising audible frequency components and ultrasonic frequency components. The transducer amplification circuit may include a first sigma-delta modulator configured to sample and quantize the amplified transducer signal to generate a first digital transducer signal comprising a first quantization noise signal. The first sigma-delta modulator may include a first noise transfer function having a high pass response in at least a portion of an audible frequency range to push the quantization noise signal to ultrasonic frequencies. A second sigma-delta modulator is configured to sample and quantize the amplified transducer signal to generate a second digital transducer signal comprising a second quantization noise signal. The second sigma-delta modulator may include a second noise transfer function with a magnitude minimum placed at the ultrasonic frequencies.

Abstract translation: 换能器放大电路可以包括具有接收换能器信号的信号输入的前置放大器电路，以提供包括可听频率分量和超声频率分量的放大的换能器信号。 换能器放大电路可以包括第一Σ-Δ调制器，其被配置为对放大的换能器信号进行采样和量化，以产生包括第一量化噪声信号的第一数字换能器信号。 第一Σ-Δ调制器可以包括在可听频率范围的至少一部分中具有高通响应的第一噪声传递函数，以将量化噪声信号推送到超声波频率。 第二Σ-Δ调制器被配置为对放大的换能器信号进行采样和量化，以产生包括第二量化噪声信号的第二数字换能器信号。 第二Σ-Δ调制器可以包括放大在超声波频率处的幅度最小的第二噪声传递函数。

公开(公告)号：US20160291618A1

公开(公告)日：2016-10-06

申请号：US14673137

申请日：2015-03-30

Applicant: Analog Devices Global

Inventor： Ulrik Sørensen Wismar ,  Khiem Quang Nguyen

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: The present invention relates in one aspect to a DC linear voltage regulator circuit for generating a regulated DC output voltage based on a DC input voltage. The DC linear voltage regulator circuit comprises a DMOS pass transistor comprising drain, gate, source and bulk terminals wherein the drain terminal is connected to a regulator output which is configured to supply the regulated DC output voltage and the source terminal is connected to a regulator input for receipt of the DC input voltage. The DC linear voltage regulator circuit comprises a switchable leakage prevention circuit, connected to the bulk terminal of the DMOS pass transistor, and configured to automatically detect and interrupt a flow of leakage current from the regulator output to the bulk terminal.

Abstract translation: 本发明在一个方面涉及一种用于基于直流输入电压产生稳定的直流输出电压的直流线性稳压器电路。 DC线性稳压器电路包括DMOS传输晶体管，其包括漏极，栅极，源极和体积端子，其中漏极端子连接到调节器输出，该稳压器输出被配置为提供稳压的DC输出电压，并且源极端子连接到调节器输入 用于接收直流输入电压。 直流线性稳压器电路包括可切换的防漏电路，连接到DMOS传输晶体管的批量端子，并被配置为自动检测和中断从稳压器输出到散装端子的漏电流。