公开(公告)号：US20230308111A1

公开(公告)日：2023-09-28

申请号：US17701742

申请日：2022-03-23

Applicant: Silicon Laboratories Inc.

Inventor： John M. Khoury

IPC: H03M3/00 ,  H03F3/183 ,  H04R3/04 ,  H04R3/02

CPC classification number: H03M3/422 ,  H03M3/356 ,  H03M3/458 ,  H03F3/183 ,  H04R3/04 ,  H04R3/02 ,  H03F2200/03

Abstract: In one embodiment, an analog-to-digital converter includes: a sum circuit to receive an analog input signal and a feedback reference signal and generate a sum signal; a feedback circuit coupled to the sum circuit to provide the feedback reference signal to the sum circuit; a filter coupled to the sum circuit to receive the sum signal and generate a filtered signal; and a punctured quantizer coupled to the filter to receive the filtered signal and quantize the filtered signal to a digital output and to output the digital output and to provide the digital output to the feedback circuit.

公开(公告)号：US09680496B2

公开(公告)日：2017-06-13

申请号：US14751063

申请日：2015-06-25

Applicant: Intel IP Corporation

Inventor： John G. Kauffman ,  Krzysztof Dufrene

IPC: H03M1/06 ,  H03M3/00 ,  H03M1/46 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M3/356 ,  H03M1/00 ,  H03M1/0607 ,  H03M1/12 ,  H03M1/46 ,  H03M3/386 ,  H03M3/424 ,  H03M3/444 ,  H03M3/454 ,  H03M3/464

Abstract: Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.

公开(公告)号：US09628104B2

公开(公告)日：2017-04-18

申请号：US14657323

申请日：2015-03-13

Applicant: Rosemount Inc.

Inventor： Rongtai Wang ,  John Paul Schulte

IPC: G01L9/12 ,  H03M3/00 ,  G01D5/24

CPC classification number: H03M3/39 ,  G01D5/24 ,  G01L9/0072 ,  G01L9/0075 ,  G01L9/12 ,  H03M3/356 ,  H03M3/376 ,  H03M3/494

Abstract: A single plate capacitance sensor includes a sensor capacitor and a reference capacitor that share common plate. A capacitance-to-digital sigma delta modulator provides separate sensor excitation and reference excitation signals to the sensor capacitor and the reference capacitor to provide high resolution detection. Programmable ratio-metric excitation voltages and adaptive excitation voltage sources can be used to enhance modulator performance.

公开(公告)号：US20170099063A1

公开(公告)日：2017-04-06

申请号：US15266458

申请日：2016-09-15

Applicant: Marvell World Trade Ltd.

Inventor： Vijay Ganwani ,  Vijay Ahirwar ,  Yui Lin ,  Sudhir Srinivasa ,  Hongyuan Zhang ,  Sridhar Narravula

IPC: H03M3/00 ,  H04L27/26 ,  H04B1/10 ,  H04L7/033

CPC classification number: H03M3/378 ,  H03M1/1085 ,  H03M1/1095 ,  H03M3/356 ,  H04B1/1036 ,  H04B2001/1063 ,  H04L7/0331 ,  H04L27/2636

Abstract: Apparatus for determining a signal-to-quantization-noise ratio of a quantization circuit includes a signal generator that generates an input test signal for input to the quantization circuit, circuitry for isolating, from output of the quantization circuit, a signal representing quantization noise, and circuitry for determining a ratio of the output of the quantization circuit to the signal representing quantization noise. The signal generator generates an analog test tone having a frequency, and the circuitry for isolating includes a notch filter filtering that frequency. Alternatively, the circuitry for isolating includes circuitry for generating a digital test signal, and a digital subtractor for subtracting the digital test signal from the output of the quantization circuit. According to another alternative, the circuitry for isolating includes a transformation circuit whose outputs represent a peak of the output of the quantization circuit and a noise floor of the output of the quantization circuit.

公开(公告)号：US09379734B2

公开(公告)日：2016-06-28

申请号：US14939679

申请日：2015-11-12

Applicant: ZENTRUM MIKROELEKTRONIK DRESDEN AG

Inventor： Raik Richter ,  Marko Mailand

IPC: H03M3/00

CPC classification number: H03M3/464 ,  H03M3/356 ,  H03M3/39 ,  H03M3/484 ,  H03M3/488

Abstract: A method and arrangement for setting an effective resolution of an output signal in an incremental delta-sigma analog-to-digital conversion by an incremental delta-sigma analog-to-digital converter, includes feeding a difference between an input signal and a reference voltage signal formed in a feedback branch to a first integrator. Safeguarding the stability of multi-stage incremental delta-sigma analog-to-digital converters for large input signal ranges and not requiring direct damping of the input signal, such that a direct SNR impairment with regard to the ADC-inherent noise sources can be avoided, is achieved by a virtual reference voltage in the feedback branch of the incremental delta-sigma analog-to-digital converter. The reference voltage signal is adapted to a changing input signal range by a settable reference capacitance and a clock cycle number dependent thereon is set.

Abstract translation: 用于通过增量Δ-Σ模数转换器设置增量Δ-Σ模数转换中的输出信号的有效分辨率的方法和装置包括馈送输入信号和参考电压之间的差 在第一积分器的反馈分支中形成的信号。 保护多级增量Δ-Σ模数转换器对于大输入信号范围的稳定性，不需要输入信号的直接阻尼，从而可以避免相对于ADC固有噪声源的直接SNR损害 ，通过增量Δ-Σ模数转换器的反馈支路中的虚拟参考电压来实现。 参考电压信号适应于可变参考电容的改变的输入信号范围，并且依赖于其的时钟周期数被设置。

公开(公告)号：US20150295587A1

公开(公告)日：2015-10-15

申请号：US14683119

申请日：2015-04-09

Applicant: ams AG

Inventor： Jose Manuel GARCIA GONZALEZ ,  Joel BERTOMEU MESTRE ,  Rafael SERRANO GOTARREDONA

IPC: H03M1/10 ,  H03M3/00 ,  H03M1/12

CPC classification number: H03M1/1019 ,  G01R27/2605 ,  H03M1/12 ,  H03M3/34 ,  H03M3/356 ,  H03M3/382 ,  H03M3/458

Abstract: A capacitance-to-digital converter (10) comprises a capacitor arrangement (30), a converter (1) that is coupled on its input side to the capacitor arrangement (30) and a calibration unit (13) that is coupled on its input side to the converter (1). The capacitor arrangement (30) comprises an input capacitor (16).

Abstract translation: 电容数字转换器（10）包括电容器装置（30），在其输入侧耦合到电容器装置（30）的转换器（1）和耦合在其输入端上的校准单元（13） （1）。 电容器装置（30）包括输入电容器（16）。

公开(公告)号：US08988260B2

公开(公告)日：2015-03-24

申请号：US13661114

申请日：2012-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Martin Kinyua

IPC: H03M3/00 ,  H03M7/30

CPC classification number: H03M7/3022 ,  H03M3/356 ,  H03M3/502

Abstract: A continuous-time delta-sigma digital-to-analog converter (DAC) includes a first delta-sigma modulator configured to quantize a most significant bit or bits of a digital input signal and produce a first quantization error signal, and a second multi-stage delta-sigma modulator configured to quantize less significant bits of the digital input signal. A first DAC is coupled to an output of the first delta-sigma modulator, and a second DAC is coupled to an output of the second noise-shaping filter. The second DAC has a greater resolution than the first DAC. A low pass output filter is coupled to a sum of an output of the first DAC and an output of the second DAC.

Abstract translation: 连续时间Δ-Σ数模转换器（DAC）包括配置为量化数字输入信号的最高有效位或产生第一量化误差信号的第一Δ-Σ调制器， 配置为量化数字输入信号的较低有效位的三级Δ-Σ调制器。 第一DAC耦合到第一Δ-Σ调制器的输出，并且第二DAC耦合到第二噪声整形滤波器的输出端。 第二个DAC具有比第一个DAC更高的分辨率。 低通输出滤波器耦合到第一DAC的输出和第二DAC的输出之和。

公开(公告)号：US08305131B2

公开(公告)日：2012-11-06

申请号：US12484469

申请日：2009-06-15

Applicant: Hae-Seung Lee

Inventor： Hae-Seung Lee

IPC: G06F7/64

CPC classification number: G11C27/026 ,  G06F7/64 ,  G11C7/06 ,  H03M1/0607 ,  H03M1/403 ,  H03M1/442 ,  H03M3/356 ,  H03M3/458

Abstract: A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.

Abstract translation: 具有有效偏移消除的过零检测器包括一组串联电容器和具有输入端子的放大器。 偏置电容器可操作地连接在放大器和串联电容器组之间。 开关可操作地连接到输入端子，并且偏移采样电容器可操作地连接到开关。 在电荷转移阶段，开关将偏移采样电容连接到放大器的输入端。

公开(公告)号：US20120242521A1

公开(公告)日：2012-09-27

申请号：US13053303

申请日：2011-03-22

Applicant: Martin KINYUA

Inventor： Martin KINYUA

IPC: H03M3/02

CPC classification number: H03M7/3022 ,  H03M3/356 ,  H03M3/502

Abstract: A continuous-time delta-sigma digital-to-analog converter (DAC) includes a first delta-sigma modulator configured to quantize a most significant bit or bits of a digital input signal and produce a first quantization error signal, and a second multi-stage delta-sigma modulator configured to quantize less significant bits of the digital input signal. A first DAC is coupled to an output of the first delta-sigma modulator, and a second DAC is coupled to an output of the second noise-shaping filter. The second DAC has a greater resolution than the first DAC. A low pass output filter is coupled to a sum of an output of the first DAC and an output of the second DAC.

Abstract translation: 连续时间Δ-Σ数模转换器（DAC）包括配置为量化数字输入信号的最高有效位或产生第一量化误差信号的第一Δ-Σ调制器， 配置为量化数字输入信号的较低有效位的三级Δ-Σ调制器。 第一DAC耦合到第一Δ-Σ调制器的输出，并且第二DAC耦合到第二噪声整形滤波器的输出端。 第二个DAC具有比第一个DAC更高的分辨率。 低通输出滤波器耦合到第一DAC的输出和第二DAC的输出之和。

公开(公告)号：US20120024221A1

公开(公告)日：2012-02-02

申请号：US13187028

申请日：2011-07-20

Applicant: Steven R. Clothier

Inventor： Steven R. Clothier

IPC: G08B7/00

CPC classification number: H03M1/0607 ,  G11C27/026 ,  H03M1/442 ,  H03M3/356 ,  H03M3/458

Abstract: A marking and signaling tool may include one or more lights and a sound generating device within a housing. A protective sheath may be positioned about the housing and permit light and/or sound to exit from the housing. An actuator may be provided to permit a user to select one of a plurality of illumination modes. One or more of the illumination modes may include the creation of sound. The housing may include a plurality of magnets for adhering the tool to a magnetic surface.

Abstract translation: 标记和信号工具可以包括一个或多个灯和在壳体内的发声装置。 保护套可以围绕壳体定位并且允许光和/或声音从壳体离开。 可以提供致动器以允许用户选择多个照明模式中的一个。 一种或多种照明模式可以包括声音的创建。 壳体可以包括用于将工具粘附到磁性表面的多个磁体。