公开(公告)号：US20190052281A1

公开(公告)日：2019-02-14

申请号：US15674985

申请日：2017-08-11

Applicant: Analog Devices Global

Inventor： Frederick Carnegie Thompson ,  Varun Agrawal ,  Jose Barreiro Silva ,  Declan M. Dalton

IPC: H03M1/08 ,  H03M1/74 ,  H03M1/06 ,  H03M1/12 ,  H03L7/089 ,  H03K5/1252 ,  H03K7/06 ,  H04L27/06

CPC classification number: H03M1/0836 ,  H03K5/1252 ,  H03K7/06 ,  H03L7/08 ,  H03L7/0893 ,  H03L2207/50 ,  H03M1/0621 ,  H03M1/1245 ,  H03M1/747 ,  H03M3/43 ,  H03M3/458 ,  H04L27/066

Abstract: This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal.

公开(公告)号：US10367516B2

公开(公告)日：2019-07-30

申请号：US15674985

申请日：2017-08-11

Applicant: Analog Devices Global

Inventor： Frederick Carnegie Thompson ,  Varun Agrawal ,  Jose Barreiro Silva ,  Declan M. Dalton

IPC: H03L7/16 ,  H03M1/08 ,  H03K5/1252 ,  H03K7/06 ,  H03L7/089 ,  H03M1/06 ,  H03M1/12 ,  H04L27/06 ,  H03M1/74 ,  H03M3/00

Abstract: This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal.