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    Method of reducing trapped holes induced by erase operations in the tunnel oxide of flash memory cells
    2.
    发明授权
    Method of reducing trapped holes induced by erase operations in the tunnel oxide of flash memory cells 有权
    减少由闪存单元的隧道氧化物中的擦除操作引起的被捕获的空穴的方法

    公开(公告)号：US06426898B1

    公开(公告)日：2002-07-30

    申请号：US09797682

    申请日：2001-03-05

    申请人： Andrei Mihnea ,  Jeffrey Kessenich ,  Chun Chen

    发明人： Andrei Mihnea ,  Jeffrey Kessenich ,  Chun Chen

    IPC分类号： G11C700

    CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445

    摘要： A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.

    摘要翻译： 公开了一种擦除闪存器件中的存储单元的方法，该闪速存储器件将通过隧道氧化物的电子重新捕获隧道氧化物中的空穴（在擦除操作之后）。 该方法使用擦除操作，擦除所有进行擦除操作的存储单元。 对过度消耗的细胞进行细胞愈合操作。 愈合操作使电子通过隧道氧化物并与被捕获的孔重组。 该复合基本上减少了隧道氧化物内的被捕获的孔，而不降低擦除操作的速度。 此外，通过减少捕获的空穴，闪存单元的电荷保持率，总体性能和耐久性显着增加。

    Program-verify method with different read and verify pass-through voltages
    3.
    发明授权
    Program-verify method with different read and verify pass-through voltages 有权
    具有不同读取和验证直通电压的程序验证方法

    公开(公告)号：US07619931B2

    公开(公告)日：2009-11-17

    申请号：US11821914

    申请日：2007-06-26

    申请人： Andrei Mihnea ,  Todd Marquart ,  Jeffrey Kessenich

    发明人： Andrei Mihnea ,  Todd Marquart ,  Jeffrey Kessenich

    IPC分类号： G11C16/06

    CPC分类号： G11C8/12 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

    摘要： Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading value from one or more memory cells in read operations.

    摘要翻译： 公开了方法和装置，这样的方法包括将验证直通电压施加到浮选存储器阵列的未选择的选择线，该选择线大于施加到未选择的选择线的读通过电压。 其他方法涉及利用单元电流来读取来自读取操作中的一个或多个存储器单元的值的单元电流低于程序验证操作中的一个或多个存储器单元的值。

    PROGRAM-VERIFY METHOD
    4.
    发明申请
    PROGRAM-VERIFY METHOD 有权
    程式验证方法

    公开(公告)号：US20100046303A1

    公开(公告)日：2010-02-25

    申请号：US12606828

    申请日：2009-10-27

    申请人： Andrei Mihnea ,  Todd Marquart ,  Jeffrey Kessenich

    发明人： Andrei Mihnea ,  Todd Marquart ,  Jeffrey Kessenich

    IPC分类号： G11C16/06

    CPC分类号： G11C8/12 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

    摘要： Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.

    摘要翻译： 公开了一些方法和装置，一些这样的方法包括将验证直通电压施加到浮动栅极存储器阵列的未选择的选择线，其大于施加到未选择的选择线的读取直通电压。 其他方法涉及在程序验证操作中利用单元电流读取来自一个或多个存储器单元的值，该单元电流低于用于在读取操作中从一个或多个存储器单元读取值的单元电流。

    Program-verify method
    5.
    发明授权
    Program-verify method 有权
    程序验证方法

    公开(公告)号：US07952936B2

    公开(公告)日：2011-05-31

    申请号：US12606828

    申请日：2009-10-27

    申请人： Andrei Mihnea ,  Todd Marquart ,  Jeffrey Kessenich

    发明人： Andrei Mihnea ,  Todd Marquart ,  Jeffrey Kessenich

    IPC分类号： G11C16/06

    CPC分类号： G11C8/12 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

    摘要： Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.

    摘要翻译： 公开了一些方法和装置，一些这样的方法包括将验证直通电压施加到浮动栅极存储器阵列的未选择的选择线，其大于施加到未选择的选择线的读取直通电压。 其他方法涉及在程序验证操作中利用单元电流读取来自一个或多个存储器单元的值，该单元电流低于用于在读取操作中从一个或多个存储器单元读取值的单元电流。

    Program-verify method
    6.
    发明申请
    Program-verify method 有权
    程序验证方法

    公开(公告)号：US20090003078A1

    公开(公告)日：2009-01-01

    申请号：US11821914

    申请日：2007-06-26

    申请人： Andrei Mihnea ,  Todd Marquart ,  Jeffrey Kessenich

    发明人： Andrei Mihnea ,  Todd Marquart ,  Jeffrey Kessenich

    IPC分类号： G11C11/34

    CPC分类号： G11C8/12 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

    摘要： Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading value from one or more memory cells in read operations.

    摘要翻译： 公开了方法和装置，这样的方法包括将验证直通电压施加到浮选存储器阵列的未选择的选择线，该选择线大于施加到未选择的选择线的读通过电压。 其他方法涉及利用单元电流来读取来自读取操作中的一个或多个存储器单元的值的单元电流低于程序验证操作中的一个或多个存储器单元的值。

    Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation
    10.
    发明授权
    Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation 失效
    非接触均匀隧道分离p-well（CUSP）非易失性存储器阵列架构，制造和操作

    公开(公告)号：US06930350B2

    公开(公告)日：2005-08-16

    申请号：US10655251

    申请日：2003-09-04

    申请人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

    发明人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

    摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

    摘要翻译： 在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。 这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。 这些阱与阵列的其他列的源/漏区隔离。 可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。