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1.发明授权Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number 失效用于传送地址，数据和控制的时间复用的直接存储器存取系统和用于串行传输编码的DMA通道号的单独的控制线
公开(公告)号：US06157970A
公开(公告)日：2000-12-05
申请号：US936318
申请日：1997-09-24
CPC分类号： G06F13/28
摘要： A system including a host coupled to a memory device and a peripheral controller device. The host is coupled to the peripheral controller device via a bus having a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device performs direct memory access (DMA) transactions with the memory device via the host and the bus.
摘要翻译： 一种包括耦合到存储器装置的主机和外围控制器装置的系统。 主机经由具有多个通用信号线的总线耦合到外围控制器装置，以承载时分复用的地址，数据和控制信息。 外围控制器设备经由主机和总线与存储器件执行直接存储器访问（DMA）事务。
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公开(公告)号：US6131127A
公开(公告)日：2000-10-10
申请号：US936303
申请日：1997-09-24
CPC分类号： G06F13/423
摘要： A system having a bus coupled to a host and a peripheral controller device each coupled to a bus. The bus includes a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device communicates with the host over the bus to control devices such as parallel port controllers, serial port controllers, super I/O controllers, floppy disk controllers, keyboard controllers and memory devices.
摘要翻译： 具有耦合到主机的总线和每个耦合到总线的外围控制器设备的系统。 总线包括多个通用信号线，用于承载时分复用的地址，数据和控制信息。 外围控制器设备通过总线与主机进行通信，以控制诸如并行端口控制器，串行端口控制器，超级I / O控制器，软盘控制器，键盘控制器和存储器设备之类的设备。
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公开(公告)号：US6119189A
公开(公告)日：2000-09-12
申请号：US936319
申请日：1997-09-24
CPC分类号： G06F13/387
摘要： A system including a host, a peripheral controller device, and a bus master device each coupled to a bus having a plurality of general purpose signal lines for carrying time-multiplexed address, data, and control information. The bus master device communicates with the host and the peripheral controller device via the bus.
摘要翻译： 一种包括主机，外围控制器设备和总线主设备的系统，每个系统耦合到具有用于承载时分复用地址，数据和控制信息的多个通用信号线的总线。 总线主机通过总线与主机和外围控制器设备进行通信。
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公开(公告)号：US6151654A
公开(公告)日：2000-11-21
申请号：US998111
申请日：1997-12-24
CPC分类号： G06F13/28 , G06F2213/3602
摘要： A method and apparatus which may be used for direct memory access (DMA) acknowledges. A method of acknowledging a request for access to a bus from a bus agent access involves receiving a request for access to the bus and generating a request acknowledge signal. The request acknowledge is generated on a multiplexed bus in response to the request for access to the bus.
摘要翻译： 可用于直接存储器访问（DMA）的方法和装置。 从总线代理接入确认访问总线的请求的方法包括接收对总线的访问请求并产生请求确认信号。 响应于访问总线的请求，在多路复用总线上产生请求确认。
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公开(公告)号：US5991841A
公开(公告)日：1999-11-23
申请号：US936848
申请日：1997-09-24
CPC分类号： G06F13/4243
摘要： A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.
摘要翻译： 具有耦合到主机和存储器装置的总线的系统。 总线可以包括多个通用信号线，以承载时分复用的地址，数据和控制信息。 存储设备可以存储系统启动信息，并通过总线与主机通信该信息。
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公开(公告)号：US07130992B2
公开(公告)日：2006-10-31
申请号：US09822684
申请日：2001-03-30
IPC分类号： G06F9/00
CPC分类号： G06F9/445 , G06F3/0601 , G06F2003/0692
摘要： The present invention is a method and system to automatic loading program on a medium into memory for execution. In one embodiment, a mode word is configured. The insertion of the medium into a drive is detected based on the mode word. A program on the medium is started when insertion is detected. In another embodiment, a polling circuit in a chipset detects the insertion of the medium into the drive. A status bit is checked in response to an interrupt generated by the polling circuit. A flag in a memory is updated based on the status bit. A poll request by an operating system is responded.
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公开(公告)号：US20160021199A1
公开(公告)日：2016-01-21
申请号：US14334105
申请日：2014-07-17
申请人： Yuri I. Krimon , David I. Poisner
发明人： Yuri I. Krimon , David I. Poisner
IPC分类号： H04L29/08
摘要： This disclosure pertains to device-monitoring systems, and in particular (but not exclusively) to detecting and deterring unauthorized use of electronic systems at distinct locations and during specific time periods. An apparatus consistent with the present disclosure includes logic, at least partially implemented in hardware, to receive an entrance message. The entrance message may include at least one policy for the manner to which a device is to be operated when present within a device restricted area. The apparatus may also include logic to send an acknowledgement notification to indicate receipt of the entrance message and an agreement to abide by the at least one policy. Furthermore, the apparatus may also include logic to detect an attempt to execute an action contrary to the at least one policy.
摘要翻译： 本公开涉及设备监视系统，并且特别地（但不排他地）用于检测和阻止在不同位置和特定时间段期间电子系统的未经授权的使用。 与本公开一致的装置包括至少部分地以硬件实现以接收入口消息的逻辑。 入口消息可以包括当设备在设备限制区域内存在时操作设备的方式的至少一个策略。 该装置还可以包括发送确认通知以指示接收入口消息和遵守该至少一个策略的协议的逻辑。 此外，该装置还可以包括用于检测执行与该至少一个策略相反的动作的尝试的逻辑。
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公开(公告)号：US20120159160A1
公开(公告)日：2012-06-21
申请号：US12974994
申请日：2010-12-21
申请人： David I. Poisner
发明人： David I. Poisner
CPC分类号： G06F21/606 , G06F21/6245 , G09C5/00 , H04L63/0471 , H04L63/0492 , H04L2209/16 , H04L2209/88
摘要： A device, method, and computer-readable medium are disclosed. In one embodiment, the device includes an inbound port to receive information from an information retrieval peripheral. The device also includes an outbound port to send information to a local computing device. The device includes masking logic to cause the local computing device to recognize the portable security device as at least one of a plurality of endpoint devices. The device also includes data obfuscation logic that is capable of obfuscating simple data format data, received from the information retrieval peripheral, obfuscating that data into a non-simple data format, and sending the obfuscated data to the local computing device. The non-simple data format includes at least one frame of video.
摘要翻译： 公开了一种设备，方法和计算机可读介质。 在一个实施例中，设备包括用于从信息检索外设接收信息的入站端口。 该设备还包括向本地计算设备发送信息的出站端口。 该设备包括屏蔽逻辑，以使本地计算设备将便携式安全设备识别为多个端点设备中的至少一个。 该设备还包括数据混淆逻辑，其能够模糊从信息检索外设接收的简单数据格式数据，将数据模糊成非简单数据格式，以及将混淆数据发送到本地计算设备。 非简单数据格式包括至少一帧视频。
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9.发明授权Method and system for using internal FIFO RAM to improve system boot times 失效使用内部FIFO RAM提高系统启动时间的方法和系统公开(公告)号：US07398383B2
公开(公告)日：2008-07-08
申请号：US11192025
申请日：2005-07-29
IPC分类号： G06F15/177
CPC分类号： G06F9/4401 , G06F9/4484 , G06F15/177
摘要： Embodiments of methods and systems for improving boot-up time in computer systems utilize RAM in devices separate from the main memory, normally dedicated to another function, to provide a stack and temporary storage during BIOS execution, enabling BIOS to call subroutines and execute in a multi-threading fashion, speeding system boot-up.
摘要翻译： 用于改善计算机系统中的启动时间的方法和系统的实施例利用与主存储器分离的设备中的RAM，通常专用于另一功能，以在BIOS执行期间提供堆栈和临时存储，使BIOS能够调用子程序并在 多线程时尚，超速系统启动。
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公开(公告)号：US20080143415A1
公开(公告)日：2008-06-19
申请号：US11642138
申请日：2006-12-18
申请人： David I. Poisner
发明人： David I. Poisner
CPC分类号： G06F1/14 , G06F11/076
摘要： A circuit, method, and system are disclosed. In one embodiment the circuit comprises a ring oscillator circuit having a plurality of delay elements, the ring oscillator circuit to generate a clock signal frequency, a checker circuit to compare a count of clock signal oscillations observed per complete loop of the ring oscillator circuit to a reference count, and to set a flag signal if the clock signal oscillation count is above a high threshold amount or below a low threshold amount.
摘要翻译： 公开了一种电路，方法和系统。 在一个实施例中，该电路包括具有多个延迟元件的环形振荡器电路，环形振荡器电路产生时钟信号频率，校验电路，用于将环形振荡器电路的每个完整环路观察到的时钟信号振荡的计数与 参考计数，并且如果时钟信号振荡计数高于高阈值量或低于低阈值量，则设置标志信号。
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