公开(公告)号：US08278684B1

公开(公告)日：2012-10-02

申请号：US11954514

申请日：2007-12-12

申请人： Andrew J. Walker ,  Helmut Puchner

发明人： Andrew J. Walker ,  Helmut Puchner

IPC分类号： H01L29/66

CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L29/0603

摘要： A voltage protection device and method is provided to prevent accidental triggering of an silicon-controlled rectifier (SCR) unless the electrostatic discharge (ESD) is at a predefined threshold above the normal power supply operating voltage or below the ground supply operating voltage. The holding voltage upon the SCR is maintained above the threshold voltage to prevent accidental triggering. The present SCR avoids use of an additional field effect transistor (FET), and avoids relying upon the breakdown of the drain terminal of the FET, but instead programs the amount of holding voltage needed above the power supply voltage using mask-programmability, fuses, or other means for maintaining the holding voltage to a desired range above the power supply voltage. The programmed holding voltage is implemented using a barrier region between the PNP and the NPN of the PNPN junctions of the SCR. In addition to or as an alternative to the barrier region, hole sink junctions can be implemented close to the anode to reduce the substrate resistance in the vicinity of the anode and, therefore, extract holes from their normal target destination.

摘要翻译： 提供了一种电压保护装置和方法，以防止硅可控整流器（SCR）的意外触发，除非静电放电（ESD）处于高于正常电源工作电压或低于接地电源工作电压的预定阈值。 SCR上的保持电压保持在阈值电压以上，以防止意外触发。 当前的SCR避免使用附加的场效应晶体管（FET），并且避免依赖于FET的漏极端子的击穿，而是使用掩模可编程性，保险丝来编程所需的高于电源电压的保持电压量， 或用于将保持电压维持在高于电源电压的期望范围的其它装置。 编程的保持电压使用PNP与SCR的PNPN结的NPN之间的屏障区域来实现。 除了作为屏障区域的替代方案之外，可以在阳极附近实现空穴接合点，以降低阳极附近的衬底电阻，并因此从其正常目标目的地提取孔。

公开(公告)号：US07659558B1

公开(公告)日：2010-02-09

申请号：US11233959

申请日：2005-09-23

申请人： Andrew J. Walker ,  Helmut Puchner

发明人： Andrew J. Walker ,  Helmut Puchner

IPC分类号： H01L21/84

CPC分类号： H01L27/0262 ,  H01L29/742 ,  H01L29/7436 ,  H01L29/87

摘要： Devices for protecting drain extended metal oxide semiconductor (DEMOS) output transistors from damage caused by electrostatic discharge (ESD) events are provided. In general, the devices include a silicon controlled rectifier (SCR) and a DEMOS transistor configured to breakdown at a lower voltage than a breakdown voltage of the output driver transistor it is configured to protect. The devices further include a pair of ohmic regions configured to trigger the SCR upon breakdown of the drain contact region of the DEMOS transistor and a collection region configured to collect charge generated by the SCR. The transistor, the pair of ohmic regions, and the SCR are respectively configured and arranged to independently set the breakdown voltage of the drain contact region, the trigger voltage of the SCR, and the holding voltage of the SCR. One of the ohmic regions may be coupled to the drain contact region of the transistor.

摘要翻译： 提供了用于保护漏极延伸金属氧化物半导体（DEMOS）输出晶体管免受静电放电（ESD）事件引起的损坏的器件。 通常，这些器件包括可控硅整流器（SCR）和配置为以比被配置为保护的输出驱动晶体管的击穿电压更低的电压来击穿的DEMOS晶体管。 器件还包括一对欧姆区域，其配置成在DEMOS晶体管的漏极接触区域击穿时触发SCR，以及被配置为收集由SCR产生的电荷的收集区域。 晶体管，一对欧姆区域和SCR分别被配置和设置为独立地设置漏极接触区域的击穿电压，SCR的触发电压和SCR的保持电压。 一个欧姆区域可以耦合到晶体管的漏极接触区域。

公开(公告)号：US07838937B1

公开(公告)日：2010-11-23

申请号：US11234255

申请日：2005-09-23

申请人： Andrew J. Walker ,  Helmut Puchner ,  Harold M. Kutz ,  James H. Shutt

发明人： Andrew J. Walker ,  Helmut Puchner ,  Harold M. Kutz ,  James H. Shutt

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L27/0262 ,  H01L29/87

摘要： Circuits including a laterally diffused output driver transistor and a distinct device configured to provide electrostatic discharge (ESD) protection for the laterally diffused output driver transistor are presented. In general, the device configured to provide ESD protection includes a drain extended metal oxide semiconductor transistor (DEMOS) transistor configured to breakdown at a lower voltage than a breakdown voltage of the laterally diffused output driver transistor. The laterally diffused output driver transistor may be a pull-down or a pull-up output driver transistor. The device also includes a silicon controlled rectifier (SCR) configured to inject charge within a semiconductor layer of the circuit upon breakdown of the DEMOS transistor. Moreover, the device includes a region configured to collect the charge injected from the SCR and further includes an ohmic contact region configured to at least partially affect the holding voltage of the SCR.

摘要翻译： 提供了包括横向扩散的输出驱动晶体管和被配置为为横向扩散输出驱动晶体管提供静电放电（ESD））保护的不同器件的电路。 通常，被配置为提供ESD保护的器件包括漏极延伸的金属氧化物半导体晶体管（DEMOS）晶体管，被配置为在比横向扩散的输出驱动晶体管的击穿电压低的电压下击穿。 横向扩散的输出驱动晶体管可以是下拉或上拉输出驱动晶体管。 该器件还包括被配置为在DEMOS晶体管击穿时在电路的半导体层内注入电荷的可控硅整流器（SCR）。 此外，该器件包括被配置为收集从SCR注入的电荷的区域，并且还包括被配置为至少部分地影响SCR的保持电压的欧姆接触区域。

公开(公告)号：US07777269B2

公开(公告)日：2010-08-17

申请号：US12142547

申请日：2008-06-19

申请人： Andrew J. Walker

发明人： Andrew J. Walker

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  G11C16/10 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/42352

摘要： A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.

公开(公告)号：US20090258462A1

公开(公告)日：2009-10-15

申请号：US12489214

申请日：2009-06-22

申请人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew J. Walker ,  Tanmay Kumar

发明人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew J. Walker ,  Tanmay Kumar

IPC分类号： H01L21/82

CPC分类号： H01L27/12 ,  H01L21/28282 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

摘要翻译： 本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。 多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。 根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。 类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

公开(公告)号：US20090087973A1

公开(公告)日：2009-04-02

申请号：US12240848

申请日：2008-09-29

申请人： Andrew J. Walker

发明人： Andrew J. Walker

IPC分类号： H01L21/3205

CPC分类号： H01L27/12 ,  H01L27/11568

摘要： A manufacturing process improves retention capabilties of dual-gate non-volatile memory cells by limiting the effects of lateral charge movement. The process limits lateral extents of the charge storage medium that is an integral part of the memory device within the dual-gate device.

摘要翻译： 通过限制横向电荷运动的影响，制造工艺提高了双栅非易失性存储单元的保留能力。 该过程限制作为双栅极器件内的存储器件的组成部分的电荷存储介质的横向范围。

公开(公告)号：US20080315294A1

公开(公告)日：2008-12-25

申请号：US12142547

申请日：2008-06-19

申请人： Andrew J. Walker

发明人： Andrew J. Walker

IPC分类号： H01L29/00

CPC分类号： H01L29/792 ,  G11C16/10 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/42352

摘要： A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.

摘要翻译： 公开了一种具有双栅极存储单元的存储电路及其制造方法。 双栅极存储单元各自包括存储器件和共享半导体层的存取器件，其各自的沟道区域设置在半导体层的不同表面上。 半导体层的厚度使得与存取装置的栅电极和存储装置之间的电相互作用相关的灵敏度参数小于预定值。 双栅极存储器单元可以用作非易失性存储器阵列的构造块，诸如由NAND串形成的存储器阵列。 在这种阵列中，在NAND串中的附近的存储器件的编程期间，在不编程的NAND串中，如果允许在半导体层中形成反转区域，或者允许半导体层电浮动， 存取装置和存储装置之间存在电相互作用以阻止存储装置的编程。

公开(公告)号：US20080283921A1

公开(公告)日：2008-11-20

申请号：US11749078

申请日：2007-05-15

申请人： Andrew J. Walker

发明人： Andrew J. Walker

IPC分类号： H01L29/78

CPC分类号： H01L21/26513 ,  H01L29/4908 ,  H01L29/78645 ,  H01L29/78648

摘要： A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located above a semiconductor or channel region in the active layer defined by spaced-apart diffusion regions formed by implanting antimony ions. The antimony-doped diffusion regions are particularly suitable in the dual-gate device because it can be implanted and activated at a temperature less than 900° C. and show little movement of the implanted antimony ions even after numerous thermal steps in the manufacturing process. As a result, dual-gate devices with well-controlled channel lengths may be achieved.

摘要翻译： 双栅极器件包括在第一栅极结构和第二栅极结构之间的有源层。 每个栅极结构通过介电层与有源层隔离，并且位于由通过注入锑离子形成的间隔扩散区限定的有源层中的半导体或沟道区的上方。 掺杂锑的扩散区域特别适用于双栅极器件，因为它可以在低于900℃的温度下被注入和激活，并且即使在制造过程中经过许多热步骤之后也不会发生注入的锑离子的移动。 因此，可以实现具有良好控制的通道长度的双栅极器件。

公开(公告)号：US07410845B2

公开(公告)日：2008-08-12

申请号：US11613102

申请日：2006-12-19

申请人： Andrew J. Walker

发明人： Andrew J. Walker

IPC分类号： H01L21/84 ,  H01L21/00 ,  H01L21/336

CPC分类号： H01L29/42344 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

摘要： A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness, such that when a pass voltage is applied to the gate electrode of the access device, the access device and the memory device remains isolated, such that the charge stored in the memory device is unaffected by the pass voltage. The pass voltage is determined from a range of voltages, when applied to the access device, has no effect on the threshold voltage of the memory device. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.

摘要翻译： 公开了一种具有双栅极存储单元的存储电路及其制造方法。 双栅极存储单元各自包括存储器件和共享半导体层的存取器件，其各自的沟道区域设置在半导体层的不同表面上。 半导体层具有厚度，使得当通路电压被施加到存取装置的栅电极时，存取装置和存储装置保持隔离，使得存储在存储装置中的电荷不受通过电压的影响。 当施加到接入装置时，从电压范围确定通过电压对存储器件的阈值电压没有影响。 双栅极存储器单元可以用作非易失性存储器阵列的构造块，诸如由NAND串形成的存储器阵列。 在这样的阵列中，在NAND串中的附近的存储器件的编程期间，在不被编程的NAND串中，如果允许在半导体层中形成反转区域，或者允许半导体层电浮动， 存取装置和存储装置之间存在电相互作用以阻止存储装置的编程。

公开(公告)号：US20080083943A1

公开(公告)日：2008-04-10

申请号：US11749094

申请日：2007-05-15

申请人： Andrew J. Walker

发明人： Andrew J. Walker

IPC分类号： H01L29/788 ,  G11C11/34 ,  H01L21/336

CPC分类号： H01L27/11568 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/42344 ,  H01L29/78645 ,  H01L29/78648

摘要： A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that electrical interaction between the access device and the memory device is characterized by a sensitivity parameter having a value within a predetermined range for a sub-threshold voltage applied to a gate electrode of the access device. To achieve good scalability of the dual-gate memory cells, the semiconductor layer between the memory device gate and access device gate can be thinned. This results in a larger sensitivity parameter but this parameter is still small enough to avoid memory charge disturbs. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.

摘要翻译： 公开了一种具有双栅极存储单元的存储电路及其制造方法。 双栅极存储单元各自包括存储器件和共享半导体层的存取器件，其各自的沟道区域设置在半导体层的不同表面上。 半导体层的厚度使得访问装置和存储装置之间的电气相互作用的特征在于对于施加到存取装置的栅电极的次级阈值电压，具有在预定范围内的值的灵敏度参数。 为了实现双栅极存储器单元的良好的可扩展性，可以减少存储器件栅极和存取器件栅极之间的半导体层。 这导致较大的灵敏度参数，但是该参数仍然足够小以避免存储器充电干扰。 双栅极存储器单元可以用作非易失性存储器阵列的构造块，诸如由NAND串形成的存储器阵列。 在这样的阵列中，在NAND串中的附近的存储器件的编程期间，在不被编程的NAND串中，如果允许在半导体层中形成反转区域，或者允许半导体层电浮动， 存取装置和存储装置之间存在电相互作用以阻止存储装置的编程。