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    Memory array incorporating memory cells arranged in NAND strings
    6.
    发明授权
    Memory array incorporating memory cells arranged in NAND strings 有权
    包含排列在NAND串中的存储单元的存储器阵列

    公开(公告)号：US07221588B2

    公开(公告)日：2007-05-22

    申请号：US10729843

    申请日：2003-12-05

    申请人： Luca G. Fasoli ,  Roy E. Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew J. Walker

    发明人： Luca G. Fasoli ,  Roy E. Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew J. Walker

    IPC分类号： G11C11/34

    CPC分类号： G11C16/04

    摘要： An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, and NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.

    摘要翻译： 示例性NAND串存储器阵列包括至少一个存储器单元平面，所述存储器单元包括薄膜可修改的电导开关器件，并且哪些单元被布置在多个串联的NAND串中，以及包括每个的串联选择器件的NAND串 结束。 另一示例性的NAND串存储器阵列包括在相同存储器块内的多于四个相邻的NAND串的组，每组相关联的不同于该组的另一个NAND串的相应全局位线。 另一示例性的NAND串存储器阵列包括与它们各自的全局位线相同的音调的NAND串。

    Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block
    7.
    发明授权
    Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block 有权
    存储器阵列，包含一个块内的镜像NAND串和非共享全局位线

    公开(公告)号：US07508714B2

    公开(公告)日：2009-03-24

    申请号：US11751567

    申请日：2007-05-21

    申请人： Luca G. Fasoli ,  Roy E. Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew J. Walker

    发明人： Luca G. Fasoli ,  Roy E. Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew J. Walker

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/04

    摘要： An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.

    摘要翻译： 示例性NAND串存储器阵列包括存储器单元的至少一个平面，所述存储器单元包括薄膜可修改的电导开关器件，并且哪些单元被布置在多个串联的NAND串中，所述NAND串包括每个的串联选择器件 结束。 另一示例性的NAND串存储器阵列包括在相同存储器块内的多于四个相邻的NAND串的组，每组相关联的不同于该组的另一个NAND串的相应全局位线。 另一示例性的NAND串存储器阵列包括与它们各自的全局位线相同的音调的NAND串。

    NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
    9.
    发明授权
    NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same 有权
    NAND存储器阵列结合未选择的存储单元中的沟道区域的电容升压及其操作方法

    公开(公告)号：US07233522B2

    公开(公告)日：2007-06-19

    申请号：US10729831

    申请日：2003-12-05

    申请人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

    发明人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1159

    摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

    摘要翻译： 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。 在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

    NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
    10.
    发明授权
    NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same 有权
    NAND存储器阵列结合未选择的存储单元中的沟道区域的电容升压及其操作方法

    公开(公告)号：US07433233B2

    公开(公告)日：2008-10-07

    申请号：US11764793

    申请日：2007-06-18

    申请人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

    发明人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1159

    摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

    摘要翻译： 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。 在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。