-
1.发明申请Non-Volatile Memory Cell with Multiple Resistive Sense Elements Sharing a Common Switching Device 有权具有多个电阻感应元件的非易失性存储器单元共享公共开关器件公开(公告)号：US20100118589A1
公开(公告)日：2010-05-13
申请号：US12424065
申请日：2009-04-15
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1675
摘要： A non-volatile memory cell array and associated method of use are disclosed. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs.
摘要翻译： 公开了一种非易失性存储单元阵列和相关联的使用方法。 根据各种实施例，阵列包括耦合到共享交换设备的多个可编程电阻感测元件（RSE）。 开关器件具有公共源极区域和多个漏极区域，每个漏极区域与所述多个RSE连接到相关联的RSE。
-
2.发明申请Non-Volatile Memory Cell with Multiple Resistive Sense Elements Sharing a Common Switching Device 有权具有多个电阻感应元件的非易失性存储器单元共享公共开关器件公开(公告)号：US20110149639A1
公开(公告)日：2011-06-23
申请号：US13037955
申请日：2011-03-01
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1675
摘要： A non-volatile memory cell array and associated method of use. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs.
摘要翻译： 非易失性存储单元阵列和相关联的使用方法。 根据各种实施例，阵列包括耦合到共享交换设备的多个可编程电阻感测元件（RSE）。 开关器件具有公共源极区域和多个漏极区域，每个漏极区域与所述多个RSE连接到相关联的RSE。
-
3.发明授权Non-volatile memory cell with multiple resistive sense elements sharing a common switching device 有权具有多个电阻感测元件的非易失性存储单元共享公共的开关器件公开(公告)号：US07933136B2
公开(公告)日：2011-04-26
申请号：US12424065
申请日：2009-04-15
IPC分类号： G11C5/06
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1675
摘要： A non-volatile memory cell array and associated method of use. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs.
摘要翻译： 非易失性存储单元阵列和相关联的使用方法。 根据各种实施例，阵列包括耦合到共享交换设备的多个可编程电阻感测元件（RSE）。 开关器件具有公共源极区域和多个漏极区域，每个漏极区域与所述多个RSE连接到相关联的RSE。
-
4.发明授权Non-volatile memory cell with multiple resistive sense elements sharing a common switching device 有权具有多个电阻感测元件的非易失性存储单元共享公共的开关器件公开(公告)号：US08861244B2
公开(公告)日：2014-10-14
申请号：US13037955
申请日：2011-03-01
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1675
摘要： A non-volatile memory cell array and associated method of use. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs.
摘要翻译： 非易失性存储单元阵列和相关联的使用方法。 根据各种实施例，阵列包括耦合到共享交换设备的多个可编程电阻感测元件（RSE）。 开关器件具有公共源极区域和多个漏极区域，每个漏极区域与所述多个RSE连接到相关联的RSE。
-
公开(公告)号：US07825478B2
公开(公告)日：2010-11-02
申请号：US12407823
申请日：2009-03-20
申请人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
发明人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
IPC分类号： H01L29/00 , H01L21/425
CPC分类号： G11C11/16 , G11C11/1659 , H01L27/228 , H01L29/1083
摘要： Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.
摘要翻译： 描述了用于电阻读出存储器的极性依赖开关。 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻式感测存储单元电连接到位触点。 源极接触和位触点用掺杂剂材料非对称地注入。
-
公开(公告)号：US20100210095A1
公开(公告)日：2010-08-19
申请号：US12774018
申请日：2010-05-05
申请人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
发明人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
IPC分类号： H01L21/425
CPC分类号： G11C11/16 , G11C11/1659 , H01L27/228 , H01L29/1083
摘要： Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.
摘要翻译： 描述了形成电阻式读出存储器的极性依赖开关的方法。 用于形成存储器单元的方法包括在源极接触中比半导体晶体管的位接触更多地注入掺杂剂材料，并且将电阻性感测存储器单元电连接到位触点。 电阻读出存储单元被配置为在电流通过电阻读出存储单元时在高电阻状态和低电阻状态之间切换。
-
公开(公告)号：US20100117160A1
公开(公告)日：2010-05-13
申请号：US12407823
申请日：2009-03-20
申请人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
发明人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
IPC分类号： H01L29/00 , H01L21/425
CPC分类号： G11C11/16 , G11C11/1659 , H01L27/228 , H01L29/1083
摘要： Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.
摘要翻译： 描述了用于电阻读出存储器的极性依赖开关。 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻式感测存储单元电连接到位触点。 源极接触和位触点用掺杂剂材料非对称地注入。
-
公开(公告)号：US08508980B2
公开(公告)日：2013-08-13
申请号：US13278334
申请日：2011-10-21
申请人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
发明人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
CPC分类号： G11C11/16 , G11C11/1659 , H01L27/228 , H01L29/1083
摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.
摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。
-
公开(公告)号：US20120039111A1
公开(公告)日：2012-02-16
申请号：US13278334
申请日：2011-10-21
申请人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
发明人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
CPC分类号： G11C11/16 , G11C11/1659 , H01L27/228 , H01L29/1083
摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.
摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。
-
公开(公告)号：US08072014B2
公开(公告)日：2011-12-06
申请号：US12903301
申请日：2010-10-13
申请人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
发明人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
CPC分类号： G11C11/16 , G11C11/1659 , H01L27/228 , H01L29/1083
摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.
摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。
-
-
-
-
-
-
-
-
-
搜索结果
241 条记录 (耗时 0.026 秒)
