公开(公告)号：US07580492B2

公开(公告)日：2009-08-25

申请号：US11151560

申请日：2005-06-13

申请人： Andrew Pickering ,  Simon Forey ,  Robert Simpson ,  Shaun Lytollis

发明人： Andrew Pickering ,  Simon Forey ,  Robert Simpson ,  Shaun Lytollis

IPC分类号： H04L7/00

CPC分类号： H04L25/069 ,  H04L7/0025 ,  H04L7/0338

摘要： Clock recovery apparatus having an early/late voter for deciding whether a current sampling point needs to be advanced or retarded, wherein the early/late voter passes and Up/Down signal to an interpolator for maintaining a clock signal; a frequency accumulator and rate multiplier 30 for generating further signals which are summed with those of the Up/Down signal of the early/late voter to provide an improved control signal to the phase interpolator. The accumulator is responsive to frequency changes in the input signal, and the interpolator acts on said Up/Down signals to adjust the clock signal by stepping it forward or backward according to control need, so that the sampling point can be advanced or retarded.

摘要翻译： 具有早/晚选民的时钟恢复装置，用于决定当前采样点是否需要提前或延迟，其中早/晚选民通过上行/下行信号到内插器，用于维持时钟信号; 频率累积器和速率倍增器30，用于产生与早/晚选民的Up / Down信号相加的信号，以向相位插值器提供改进的控制信号。 累加器响应于输入信号中的频率变化，并且内插器作用于所述上/下信号，以根据控制需要向前或向后逐步调整时钟信号，使得采样点可以提前或延迟。

公开(公告)号：US20060002498A1

公开(公告)日：2006-01-05

申请号：US11151560

申请日：2005-06-13

申请人： Andrew Pickering ,  Simon Forey ,  Robert Simpson ,  Shaun Lytollis

发明人： Andrew Pickering ,  Simon Forey ,  Robert Simpson ,  Shaun Lytollis

IPC分类号： H04L27/06

CPC分类号： H04L25/069 ,  H04L7/0025 ,  H04L7/0338

摘要： There is provided a Clock recovery apparatus comprising: an early/late voter for deciding whether a current sampling point needs to be advanced or retarded, wherein said early/late voter passes an Up/Down signal to an interpolator for maintaining a clock signal; a frequency accumulator and rate multiplier 30 for generating further signals which are summed with those of the Up/Down signal of the early/late voter to provide an improved control signal to the phase interpolator. The accumulator is responsive to frequency changes in the input signal, and said interpolator acts on said Up/Down signals to adjust the clock signal by stepping it forward or backward according to control need, so that said sampling point can be advanced or retarded.

摘要翻译： 提供了一种时钟恢复装置，包括：早/晚选民，用于决定当前采样点是否需要提前或延迟，其中所述早/晚选民将向上/向下信号传递到内插器以维持时钟信号; 频率累积器和速率倍增器30，用于产生与早/晚选民的Up / Down信号相加的信号，以向相位插值器提供改进的控制信号。 累加器响应于输入信号中的频率变化，并且所述内插器作用于所述上/下信号，以根据控制需要向前或向后逐步地调整时钟信号，使得所述采样点可以被提前或延迟。

公开(公告)号：US20050102593A1

公开(公告)日：2005-05-12

申请号：US10704288

申请日：2003-11-07

申请人： Jesse Ko ,  Shaun Lytollis

发明人： Jesse Ko ,  Shaun Lytollis

IPC分类号： G01R31/317 ,  G01R31/28

CPC分类号： G01R31/31716

摘要： System and method are implemented to allow phase lock loop (PLL) status testing during a Serializer/Deserializer (SERDES) internal loopback built-in self-test (BIST). An existing pseudo random binary sequence (PRBS) data generator is modified to include a mode that produces a data pattern having a frequency content low enough to be verified on the tester used at the probe.

摘要翻译： 实现系统和方法，以便在串行器/解串器（SERDES）内部回送内置自检（BIST）期间允许锁相环（PLL）状态测试。 现有的伪随机二进制序列（PRBS）数据生成器被修改为包括产生具有足够低的频率内容的数据模式的模式，以便在探测器使用的测试仪上进行验证。

公开(公告)号：US20080212718A1

公开(公告)日：2008-09-04

申请号：US12028433

申请日：2008-02-08

申请人： Shaun Lytollis

发明人： Shaun Lytollis

IPC分类号： H04L27/06

CPC分类号： H03G3/002

摘要： A multi-rate tracking circuit with an input for a signal, an output arranged to indicate a current proposed level related to the signal, and voting logic connected to the input, arranged to indicate of a direction of change in the current proposed level. A first counter is connected to the voting logic, and arranged to vary the current proposed level based on the indications received from the voting logic. A second counter is arranged to vary a value based on the indications from the voting logic. The variation of the current proposed level by the first counter is dependent on the value varied by the second counter.

摘要翻译： 一种具有用于信号的输入的多速率跟踪电路，被布置为指示与信号相关的当前提出的电平的输出以及连接到输入的投票逻辑，被布置为指示当前提出的电平的变化方向。 第一计数器连接到投票逻辑，并且被布置为基于从投票逻辑接收到的指示来改变当前提议的等级。 第二计数器被布置为基于来自投票逻辑的指示来改变值。 当前提出的电平由第一计数器的变化取决于由第二计数器变化的值。

公开(公告)号：US20080195363A1

公开(公告)日：2008-08-14

申请号：US12028448

申请日：2008-02-08

申请人： Shaun Lytollis

发明人： Shaun Lytollis

IPC分类号： G06G7/48

CPC分类号： G06F17/5036

摘要： An analogue signal modelling routine for a hardware description language, wherein an output providing an analogue signal is represented by a value stored in an output variable, an input accepting the analogue signal is represented by a value stored in an input variable, and the routine is arranged to update the value stored in the input variable when the value stored on the output value is changed. The level of an analogue signal can be represented using a floating point number.

摘要翻译： 一种用于硬件描述语言的模拟信号建模程序，其中提供模拟信号的输出由存储在输出变量中的值表示，接受模拟信号的输入由存储在输入变量中的值表示，并且例程是 被布置成当存储在输出值上的值改变时更新存储在输入变量中的值。 可以使用浮点数来表示模拟信号的电平。

公开(公告)号：US07146284B2

公开(公告)日：2006-12-05

申请号：US10704288

申请日：2003-11-07

申请人： Jesse Jonghyuk Ko ,  Shaun Lytollis

发明人： Jesse Jonghyuk Ko ,  Shaun Lytollis

IPC分类号： G06F19/00

CPC分类号： G01R31/31716

摘要： System and method are implemented to allow phase lock loop (PLL) status testing during a Serializer/Deserializer (SERDES) internal loopback built-in self-test (BIST). An existing pseudo random binary sequence (PRBS) data generator is modified to include a mode that produces a data pattern having a frequency content low enough to be verified on the tester used at the probe.

摘要翻译： 实现系统和方法，以便在串行器/解串器（SERDES）内部回送内置自检（BIST）期间允许锁相环（PLL）状态测试。 现有的伪随机二进制序列（PRBS）数据生成器被修改为包括产生具有足够低的频率内容的数据模式的模式，以便在探测器使用的测试仪上进行验证。

公开(公告)号：US20080191774A1

公开(公告)日：2008-08-14

申请号：US12028415

申请日：2008-02-08

申请人： Shaun Lytollis

发明人： Shaun Lytollis

IPC分类号： G06F1/04

CPC分类号： H03K21/08 ,  G06F1/06 ,  H03K21/40 ,  H03K23/68 ,  H03L7/0995

摘要： A clock circuit with a plurality of inputs for a plurality of respective clock signals, the clock signals alternating between a first and a second state. At least one divider circuit is arranged to take an input clock signal and provide an output that is in the first state for a first fixed multiple of the duration the clock signal is in the first state, and in the second state for a second fixed multiple of the duration the clock signal is in the second state. A plurality of delay circuits are arranged to take the output of the divider circuit or circuits and provide a set of outputs each delayed by a fixed duration. A selection circuit is arranged to select the outputs of the delay circuits in sequence. The selection circuit is arranged to select the next output in the sequence at or after the time when the selected output changes from the first state to the second state.

摘要翻译： 具有用于多个相应时钟信号的多个输入的时钟电路，所述时钟信号在第一和第二状态之间交替。 至少一个分频器电路被布置成获取输入时钟信号并提供处于第一状态的输出，用于时钟信号处于第一状态的持续时间的第一固定倍数，并且在第二状态中提供第二固定倍数 在时钟信号处于第二状态的持续时间内。 多个延迟电路被布置成取得分频器电路或电路的输出，并提供一组每个延迟固定持续时间的输出。 选择电路被布置成依次选择延迟电路的输出。 选择电路被配置为在所选择的输出从第一状态变为第二状态的时间期间或之后选择序列中的下一个输出。

公开(公告)号：US5604888A

公开(公告)日：1997-02-18

申请号：US224148

申请日：1994-04-07

申请人： Bijan Kiani-Shabestari ,  John Dunn ,  Shaun Lytollis

发明人： Bijan Kiani-Shabestari ,  John Dunn ,  Shaun Lytollis

IPC分类号： G06F17/50 ,  G06F17/00 ,  G06F13/00

CPC分类号： G06F17/5027

摘要： The use of daughterboards connecting to a motherboard in an emulation system allows for the upgrading of the emulation field programmable gate arrays in the system, and for the use of different types of field programmable gate arrays. These changes can be made without changing the motherboard. The motherboard has sockets which have pin locations which are allocated to interconnect structures and to an emulation bus. The chips on the cards can contain different emulation field programmable gate arrays, or could contain core chips, which can be directly connected to the motherboard through the daughterboards. The daughterboards connect the emulation FPGAs and the core chips to the correct pin locations of the sockets. Controller chips on the cards allow for different types of field programmable gate arrays to be used and simplify the configuration loading and debugging of the system. Additionally, the present system includes a system using a reconfigurable interface in a controller chip. This reconfigurable interface allows for different types of field programmable gate arrays to be used in the emulation system.

摘要翻译： 在仿真系统中使用连接到母板的子板允许升级系统中的仿真现场可编程门阵列，并且用于使用不同类型的现场可编程门阵列。 这些更改可以在不更改主板的情况下进行。 主板具有插座，这些插座具有分配给互连结构和仿真总线的引脚位置。 卡上的芯片可以包含不同的仿真现场可编程门阵列，或者可以包含核心芯片，可以通过子板直接连接到主板。 子板将仿真FPGA和核心芯片连接到插座的正确引脚位置。 卡上的控制器芯片允许使用不同类型的现场可编程门阵列，并简化系统的配置加载和调试。 此外，本系统包括在控制器芯片中使用可重配置接口的系统。 该可重构接口允许在仿真系统中使用不同类型的现场可编程门阵列。