公开(公告)号：US06815986B2

公开(公告)日：2004-11-09

申请号：US10196622

申请日：2002-07-16

申请人： Aninda Roy ,  Claude Gauthier ,  Brian Amick ,  Dean Liu

发明人： Aninda Roy ,  Claude Gauthier ,  Brian Amick ,  Dean Liu

IPC分类号： H03L706

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0891

摘要： A delay locked loop implementing design-for-test features to test for, among other, stuck-at-faults is provided. The delay locked loop uses multiplexers as design-for-test devices for controllability purposes and flip-flops as design-for-test devices for observability purposes. Such implementation of design-for-test features within a delay locked loop allows for pre-packaging delay locked loop verification and testing.

摘要翻译： 提供了一种实现设计测试功能的延迟锁定环路，用于测试其他故障中的故障。 延迟锁定环使用多路复用器作为可测试性设计的测试设备和作为用于可观测目的的用于测试设备的触发器。 这种延迟锁定环路内的设计测试功能的实现允许预包装延迟锁定环验证和测试。

公开(公告)号：US06909203B2

公开(公告)日：2005-06-21

申请号：US10356905

申请日：2003-02-03

申请人： Claude Gauthier ,  Brian Amick ,  Aninda Roy

发明人： Claude Gauthier ,  Brian Amick ,  Aninda Roy

IPC分类号： G06F1/26 ,  H02H7/00 ,  A01H79/00

CPC分类号： G06F1/26 ,  Y10T307/398

摘要： A method and apparatus for regulating resonance in a computer system I/O interface is provided. A shunting impedance/resistance is arranged across a power supply of the I/O interface. The shunting impedance/resistance is controlled by circuitry that is arranged to detect voltage overshoot conditions in the I/O interface. The circuitry has (1) an analog front end that is arranged to detect power supply oscillations relative to a grounded terminal, (2) an amplifier (or logic conversion circuit) that is arranged to convert an output signal from the analog front end to a digital signal, and (3) a shunting apparatus arranged to modify power supply behavior in the I/O interface dependent on the digital signal.

摘要翻译： 提供了一种用于调节计算机系统I / O接口中的共振的方法和装置。 在I / O接口的电源上布置分流阻抗/电阻。 分流阻抗/电阻由设置为检测I / O接口中的电压过冲条件的电路控制。 电路具有（1）模拟前端，其被配置为检测相对于接地端子的电源振荡，（2）放大器（或逻辑转换电路），其被布置为将来自模拟前端的输出信号转换为 数字信号，以及（3）分配装置，其被配置为根据数字信号修改I / O接口中的电源行为。

公开(公告)号：US06597218B1

公开(公告)日：2003-07-22

申请号：US10131308

申请日：2002-04-24

申请人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

发明人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

IPC分类号： H03L706

CPC分类号： H03L7/0891 ,  H03L7/0812 ,  Y10S331/02

摘要： A technique Readjusting a bias-generator in a delay locked loop after fabrication of the delay locked loop. The technique involves use of an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated.

摘要翻译： 一种技术在制造延迟锁定环路后，在延迟锁定环路中重新调整偏置发生器。 该技术涉及使用可操作地连接到偏置发生器的调节电路，其中调节电路是可控制的，以便于修正偏置发生器的电压输出。 由偏置发生器输出的电压的这种控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路性能特性。

公开(公告)号：US06806698B2

公开(公告)日：2004-10-19

申请号：US10078945

申请日：2002-02-19

申请人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Dean Liu ,  Kamran Zarrineh ,  Pradeep Trivedi

发明人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Dean Liu ,  Kamran Zarrineh ,  Pradeep Trivedi

IPC分类号： G01R2314

CPC分类号： H03M1/0621 ,  G01K7/01 ,  G01K7/32 ,  H03M1/60

摘要： A method and apparatus that uses the difference between two nodal voltages, such as a temperature-independent voltage and a temperature-dependent voltage, to determine the actual temperature at a point on an integrated circuit is provided. Further, a method and apparatus that converts a difference between nodal voltages in an integrated circuit from an analog to a digital quantity on the integrated circuit such that the difference in voltage may be used by an on-chip digital system is provided. Further, a method and apparatus for quantifying a difference in voltage between a first node and a second node of a temperature sensor is provided.

摘要翻译： 提供了使用两个节点电压之间的差异的方法和装置，例如与温度无关的电压和与温度有关的电压，以确定集成电路上的点处的实际温度。 此外，提供了一种将集成电路中的节点电压与集成电路中的数字量之间的差异转换为使得片上数字系统可以使用电压差的方法和装置。 此外，提供了用于量化温度传感器的第一节点和第二节点之间的电压差的方法和装置。

公开(公告)号：US06704680B2

公开(公告)日：2004-03-09

申请号：US10075205

申请日：2002-02-14

申请人： Brian Amick ,  Claude Gauthier ,  Pradeep Trivedi ,  Dean Liu

发明人： Brian Amick ,  Claude Gauthier ,  Pradeep Trivedi ,  Dean Liu

IPC分类号： G05F302

CPC分类号： G06F17/5036 ,  G01K15/00 ,  G06F17/5063

摘要： A method for optimizing a decoupling capacitance for an on-chip temperature sensor is provided. A representative power supply waveform having noise is input into a simulation of the on-chip temperature sensor; a difference between a temperature representative input and a temperature dependent output of the on-chip temperature sensor is determined; and an amount of the decoupling capacitance is adjusted until the difference falls below a pre-selected value. A computer system for optimizing a decoupling capacitance for an on-chip temperature sensor is also provided. A computer-readable medium having recorded thereon instructions executable by a processor for optimizing a decoupling capacitance for an on-chip temperature sensor is further provided.

摘要翻译： 提供了一种用于优化片上温度传感器的去耦电容的方法。 将具有噪声的代表性电源波形输入到片上温度传感器的仿真中; 确定温度代表性输入和片上温度传感器的与温度相关的输出之间的差异; 并且调整去耦电容的量，直到差降低到预选值以下。 还提供了一种用于优化片上温度传感器的去耦电容的计算机系统。 还提供了一种其上记录有可由处理器执行以用于优化用于片上温度传感器的去耦电容的指令的计算机可读介质。

公开(公告)号：US06593784B1

公开(公告)日：2003-07-15

申请号：US10131299

申请日：2002-04-24

申请人： Claude Gauthier ,  Brian Amick ,  Pradeep Trivedi ,  Dean Liu

发明人： Claude Gauthier ,  Brian Amick ,  Pradeep Trivedi ,  Dean Liu

IPC分类号： H03L706

CPC分类号： H03L7/0893 ,  H03L7/18

摘要： A technique for adjusting a bias-generator in a phase locked loop after fabrication of the phase locked loop is provided. The technique involves use of an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated.

摘要翻译： 提供了一种用于在锁相环制造之后在锁相环中调整偏压发生器的技术。 该技术涉及使用可操作地连接到偏置发生器的调节电路，其中调节电路是可控制的，以便于修正偏置发生器的电压输出。 由偏置发生器输出的电压的这种控制允许设计者在制造了锁相环之后实现期望的锁相环性能特性。

公开(公告)号：US06691291B2

公开(公告)日：2004-02-10

申请号：US10075320

申请日：2002-02-14

申请人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

发明人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method for estimating jitter in a delay locked loop is provided. The estimation is determined from a simulation that uses a representative power supply waveform having noise as an input. Further, a computer system for estimating jitter in a delay locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to estimate jitter in a delay locked loop is provided.

摘要翻译： 提供了一种用于估计延迟锁定环路中的抖动的方法。 从使用具有噪声的代表性电源波形作为输入的仿真确定估计。 此外，提供了一种用于估计延迟锁定环路中的抖动的计算机系统。 此外，提供了其上记录有适于估计延迟锁定环路中的抖动的指令的计算机可读介质。

公开(公告)号：US06784752B2

公开(公告)日：2004-08-31

申请号：US10131288

申请日：2002-04-24

申请人： Claude Gauthier ,  Brian Amick ,  Pradeep Trivedi ,  Dean Liu

发明人： Claude Gauthier ,  Brian Amick ,  Pradeep Trivedi ,  Dean Liu

IPC分类号： H03B500

CPC分类号： G06F1/10 ,  H03L7/081 ,  H03L7/18

摘要： A phase locked loop that includes a receiver that is adjustable to substantially match delay of a system clock and a feedback clock at an input of the phase locked loop is provided. The receiver employs system clock path circuitry to input the system clock and feedback clock path circuitry to input the feedback clock, where current flow and load resistances associated with the system clock path circuitry and current flow and load resistances associated with the feedback clock path circuitry are responsive to one or more bias signals that are adjustable using one or more adjustment circuits that are operatively connected to the receiver. The control of the one or more bias signals via the one or more adjustment circuits facilitates the generation of substantially delay matched system and feedback clocks.

摘要翻译： 提供了一种锁相环，其包括可调整以基本上匹配系统时钟的延迟的接收器和在锁相环的输入处的反馈时钟。 接收机采用系统时钟路径电路来输入系统时钟和反馈时钟路径电路以输入反馈时钟，其中与系统时钟路径电路相关联的电流和负载电阻以及与反馈时钟路径电路相关联的电流和负载电阻是 响应于使用可操作地连接到接收器的一个或多个调节电路可调整的一个或多个偏置信号。 通过一个或多个调整电路对一个或多个偏置信号的控制有助于产生基本上延迟匹配的系统和反馈时钟。

公开(公告)号：US06687881B2

公开(公告)日：2004-02-03

申请号：US10075782

申请日：2002-02-14

申请人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

发明人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method for optimizing loop bandwidth in a delay locked loop is provided. A representative power supply waveform having noise is input into a simulation of the delay locked loop; an estimate of jitter is determined; and the loop bandwidth of the delay looked loop is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing loop bandwidth in a delay locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize loop bandwidth in a delay locked loop is provided.

摘要翻译： 提供了一种用于优化延迟锁定环路中环路带宽的方法。 具有噪声的代表性电源波形被输入到延迟锁定环路的仿真中; 确定抖动的估计; 并且调整延迟看环路的环路带宽，直到抖动下降到低于预选值。 此外，提供了一种用于优化延迟锁定环路中的环路带宽的计算机系统。 此外，提供了其上记录有适于优化延迟锁定环路中的环路带宽的指令的计算机可读介质。

公开(公告)号：US06664831B2

公开(公告)日：2003-12-16

申请号：US10131687

申请日：2002-04-24

申请人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

发明人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

IPC分类号： H03L706

CPC分类号： H03L7/0898 ,  H03L7/0812 ,  H03L7/0896

摘要： A charge pump design that facilitates post-fabrication control of delay locked loop charge pump current is provided. The charge pump includes an adjustment device responsive to user controlled signals that are varied to achieve a desired amount of charge pump current. Such control of the charge pump current in a delay locked loop allows a designer to achieve a desired DLL performance characteristic after the DLL has been fabricated.

摘要翻译： 提供了一种有助于延迟锁定环电荷泵电流的制造后控制的电荷泵设计。 电荷泵包括响应用户控制的信号的调节装置，其被改变以实现所需量的电荷泵电流。 在延迟锁定环路中对电荷泵电流的这种控制允许设计者在DLL被制造之后实现期望的DLL性能特性。