公开(公告)号：US07146303B2

公开(公告)日：2006-12-05

申请号：US10376753

申请日：2003-02-28

申请人： Aninda Roy ,  Vipul Parikh

发明人： Aninda Roy ,  Vipul Parikh

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022

摘要： A technique for incorporating power information in a register transfer level design involves defining a module representing an integrated circuit block having its own power grid. The integrated circuit block, when in a power off mode effectuated by a deactivation of a clock signal to the integrated circuit, uses a device dependent on a power grid of an adjoining integrated circuit block to preserve output information from the integrated circuit block to the adjoining integrated circuit block.

摘要翻译： 用于将功率信息并入寄存器传送级设计的技术涉及定义表示具有其自己的电网的集成电路块的模块。 集成电路块在通过对集成电路的时钟信号的去激活而处于断电模式的情况下使用依赖于相邻集成电路块的电网的设备来将集成电路块的输出信息保留到相邻的 集成电路块。

公开(公告)号：US20070099572A1

公开(公告)日：2007-05-03

申请号：US11263791

申请日：2005-10-31

申请人： Navindra Navaratnam ,  Aninda Roy

发明人： Navindra Navaratnam ,  Aninda Roy

IPC分类号： H04B17/00 ,  H04B1/28

CPC分类号： H04B3/46

摘要： In some embodiments, a chip with a transmitter having a transmitter driver is provided. Also provided is a general compensation circuit coupled to the transmitter to generally compensate the transmitter driver and a specific compensation circuit coupled to the transmitter driver to specifically compensate the transmitter driver. Other embodiments are disclosed and claimed herein.

摘要翻译： 在一些实施例中，提供具有发射机的具有发射机驱动器的芯片。 还提供了耦合到发射器的通用补偿电路，以大体上补偿发射器驱动器和耦合到发射器驱动器的特定补偿电路，以特别地补偿发射器驱动器。 本文公开和要求保护的其它实施例。

公开(公告)号：US06909203B2

公开(公告)日：2005-06-21

申请号：US10356905

申请日：2003-02-03

申请人： Claude Gauthier ,  Brian Amick ,  Aninda Roy

发明人： Claude Gauthier ,  Brian Amick ,  Aninda Roy

IPC分类号： G06F1/26 ,  H02H7/00 ,  A01H79/00

CPC分类号： G06F1/26 ,  Y10T307/398

摘要： A method and apparatus for regulating resonance in a computer system I/O interface is provided. A shunting impedance/resistance is arranged across a power supply of the I/O interface. The shunting impedance/resistance is controlled by circuitry that is arranged to detect voltage overshoot conditions in the I/O interface. The circuitry has (1) an analog front end that is arranged to detect power supply oscillations relative to a grounded terminal, (2) an amplifier (or logic conversion circuit) that is arranged to convert an output signal from the analog front end to a digital signal, and (3) a shunting apparatus arranged to modify power supply behavior in the I/O interface dependent on the digital signal.

摘要翻译： 提供了一种用于调节计算机系统I / O接口中的共振的方法和装置。 在I / O接口的电源上布置分流阻抗/电阻。 分流阻抗/电阻由设置为检测I / O接口中的电压过冲条件的电路控制。 电路具有（1）模拟前端，其被配置为检测相对于接地端子的电源振荡，（2）放大器（或逻辑转换电路），其被布置为将来自模拟前端的输出信号转换为 数字信号，以及（3）分配装置，其被配置为根据数字信号修改I / O接口中的电源行为。

公开(公告)号：US07433396B2

公开(公告)日：2008-10-07

申请号：US10112302

申请日：2002-03-28

申请人： Aninda Roy

发明人： Aninda Roy

IPC分类号： H03K5/159

CPC分类号： G11C7/1048 ,  G11C2207/2254

摘要： Disclosed are novel methods and apparatus for efficiently providing equalization in single-ended chip-to-chip communication. In an embodiment, a method of adjusting signal levels to provide improved communication between a sender device and a receiver device is disclosed. The method includes providing a plurality of voltage dividers. The plurality of voltage dividers may be coupled to each other to provide a reference voltage to the receiver device. The method further includes providing a storage device to store previously received data by the receiver device and providing a controller to selectively activate the plurality of voltage dividers.

摘要翻译： 公开了用于在单端芯片到芯片通信中有效提供均衡的新颖方法和装置。 在一个实施例中，公开了一种调整信号电平以提供发送器设备和接收器设备之间改进的通信的方法。 该方法包括提供多个分压器。 多个分压器可以彼此耦合以向接收器装置提供参考电压。 该方法还包括提供存储设备以存储接收机设备先前接收到的数据，并提供控制器以选择性地激活多个分压器。

公开(公告)号：US06664850B1

公开(公告)日：2003-12-16

申请号：US10027799

申请日：2001-12-19

申请人： Aninda Roy

发明人： Aninda Roy

IPC分类号： H03F102

CPC分类号： G11C7/1093 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222

摘要： A method for reducing delay variability in a differential receiver includes receiving a plurality of differential input signals, determining a first transition delay time of an output in response to the plurality of differential input signals, determining a second transition delay time of the output in response to the plurality of differential input signals, and modifying capacitance coupled to the output in response to the first transition delay time and to the second transition delay time.

摘要翻译： 一种用于减小差分接收机中的延迟变化的方法，包括接收多个差分输入信号，响应于所述多个差分输入信号确定输出的第一转换延迟时间，响应于所述差分输入信号确定所述输出的第二转换延迟时间 所述多个差分输入信号，以及响应于所述第一转换延迟时间和所述第二转换延迟时间而修改耦合到所述输出的电容。

公开(公告)号：US06658061B1

公开(公告)日：2003-12-02

申请号：US10027812

申请日：2001-12-19

申请人： Aninda Roy

发明人： Aninda Roy

IPC分类号： H04B300

CPC分类号： H04L25/061 ,  H04L7/0008

摘要： A method for receiving data from a sending system in a receiving system includes receiving a pair of differential clock signals from the sending system, determining a reference voltage in the receiving system in response to the pair of differential clock signals, receiving a test data signal from the sending system, adjusting the reference voltage to form an updated reference voltage in response to the test data signal, receiving a single-ended data signal from the sending system relative to a reference voltage and determining a data signal in response to the single-ended data signal and to the updated reference voltage.

摘要翻译： 一种用于在接收系统中从发送系统接收数据的方法包括从发送系统接收一对差分时钟信号，响应于该对差分时钟信号确定接收系统中的参考电压，从第 所述发送系统响应于所述测试数据信号调整所述参考电压以形成更新的参考电压，从所述发送系统接收相对于参考电压的单端数据信号，并响应于所述单端数据信号确定数据信号 数据信号和更新的参考电压。

公开(公告)号：US06388495B1

公开(公告)日：2002-05-14

申请号：US09791337

申请日：2001-02-23

申请人： Aninda Roy ,  Gajendra P. Singh

发明人： Aninda Roy ,  Gajendra P. Singh

IPC分类号： H03K508

CPC分类号： G06F13/4086 ,  H03K5/08

摘要： The present invention is directed to an apparatus and method to clamp and terminate signals along a communication bus; the clamping and termination are performed dynamically whenever a signal exceeds a set peak value or falls below a set low value. Variations include a clamping and termination circuit made of metal oxide semiconductor (MOS) devices where one MOS device clamps for over-voltage and another MOS device clamps for under-voltage. Biasing circuits to the gates of the MOS devices assure that proper bias voltage is applied so that the MOS devices only clamp and terminate when a signal is received and that signal falls off the set high or low values, this assures dynamic clamping and termination and avoids unnecessary additional voltage from a driving device.

摘要翻译： 本发明涉及一种沿着通信总线钳位和终止信号的装置和方法; 每当信号超过设定的峰值或低于设定的低值时，动作执行钳位和终止。 变化包括由金属氧化物半导体（MOS）器件制成的钳位和终端电路，其中一个MOS器件钳位用于过电压，另一个MOS器件钳位用于欠压。 偏置电路到MOS器件的栅极确保施加适当的偏置电压，使得MOS器件仅在接收到信号时钳位并终止该信号，并且该信号从设定的高或低值下降，这确保动态钳位和终止，并避免 来自驱动装置的不必要的附加电压。

公开(公告)号：US06815986B2

公开(公告)日：2004-11-09

申请号：US10196622

申请日：2002-07-16

申请人： Aninda Roy ,  Claude Gauthier ,  Brian Amick ,  Dean Liu

发明人： Aninda Roy ,  Claude Gauthier ,  Brian Amick ,  Dean Liu

IPC分类号： H03L706

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0891

摘要： A delay locked loop implementing design-for-test features to test for, among other, stuck-at-faults is provided. The delay locked loop uses multiplexers as design-for-test devices for controllability purposes and flip-flops as design-for-test devices for observability purposes. Such implementation of design-for-test features within a delay locked loop allows for pre-packaging delay locked loop verification and testing.

摘要翻译： 提供了一种实现设计测试功能的延迟锁定环路，用于测试其他故障中的故障。 延迟锁定环使用多路复用器作为可测试性设计的测试设备和作为用于可观测目的的用于测试设备的触发器。 这种延迟锁定环路内的设计测试功能的实现允许预包装延迟锁定环验证和测试。

公开(公告)号：US06791360B2

公开(公告)日：2004-09-14

申请号：US10241202

申请日：2002-09-11

申请人： Claude R. Gauthier ,  Brian W. Amick ,  Aninda Roy

发明人： Claude R. Gauthier ,  Brian W. Amick ,  Aninda Roy

IPC分类号： H03K1900

CPC分类号： H03L7/07 ,  G06F9/3869 ,  H03K5/133 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0012 ,  H04L7/0041

摘要： A source synchronous interface determines an amount of delay for an incoming data signal and a phase offset for a latch device that latches the incoming data signal. A delay locked loop may be a dual loop delay locked loop, in which case, the loops may use a low jitter, local clock signal and an input clock signal that was transmitted with the data signal. The low jitter, local clock signal may provide a stable source from which to derive good clock signal edge transitions. The input clock signal may be used to determine the long term clock signal drift. A finite state machine within the dual loop delay locked loop may provide the necessary information for the amount of delay and the phase offset. The delay of the incoming data signal is produced by a digital delay line.

公开(公告)号：US07043683B2

公开(公告)日：2006-05-09

申请号：US10360312

申请日：2003-02-07

申请人： Brian W. Amick ,  Claude R. Gauthier ,  Aninda Roy

发明人： Brian W. Amick ,  Claude R. Gauthier ,  Aninda Roy

IPC分类号： G03M13/00 ,  G01R31/28

CPC分类号： G06F1/3209 ,  H04J3/06 ,  H04L7/0037

摘要： A data transmission update technique for use in a low power mode and/or a low activity mode of a computer system or a portion thereof is provided. When in the low power mode and/or the low activity mode, the technique initiates a testing of data transmissions, the results of which are used to adjust the timing of data receipt such that accurate and timely date communications are facilitated.

摘要翻译： 提供了一种用于计算机系统的低功率模式和/或低活动模式的数据传输更新技术或其一部分。 当处于低功率模式和/或低活动模式时，该技术启动对数据传输的测试，其结果用于调整数据接收的时间，以便促进准确和及时的日期通信。