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    System initialization of microcode-based memory built-in self-test
    2.
    发明授权
    System initialization of microcode-based memory built-in self-test 失效
    基于微代码的内存系统初始化内置自检

    公开(公告)号：US06874111B1

    公开(公告)日：2005-03-29

    申请号：US09625996

    申请日：2000-07-26

    申请人： R. Dean Adams ,  Thomas J. Eckenrode ,  Steven L. Gregor ,  Kamran Zarrineh

    发明人： R. Dean Adams ,  Thomas J. Eckenrode ,  Steven L. Gregor ,  Kamran Zarrineh

    IPC分类号： G01R31/28 ,  G06F12/16 ,  G11C29/12 ,  G11C29/16

    CPC分类号： G11C29/16 ,  G11C2029/0401

    摘要： The functionality of a programmable memory built-in self-test (BIST) arrangement for testing an embedded memory structure of an integrated circuit is extended to system level testing to ascertain operability of the system after the integrated circuits and boards including them have been placed in service in larger systems, by generating default test signals which are loaded in an instruction store module when test instructions are not provided from an external tester. This additional utility of the BIST arrangement, increases efficiency of chip space utilization and improves the system level test. Loading of test instructions from an external tester during chip manufacture and/or board assembly is unaffected.

    摘要翻译： 用于测试集成电路的嵌入式存储器结构的可编程存储器内置自检（BIST）布置的功能被扩展到系统级测试，以在集成电路和包括它们的板被放置在其中之后确定系统的可操作性 通过生成在外部测试仪不提供测试指令时加载到指令存储模块中的默认测试信号，可以在更大的系统中进行服务。 BIST安排的这一附加功能可以提高芯片空间利用效率，并提高系统级测试。 在芯片制造和/或电路板组装期间从外部测试仪装载测试指令不受影响。

    Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors
    3.
    发明授权
    Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors 有权
    用于高性能微处理器的高效存储器内置自检架构的方法和装置

    公开(公告)号：US07260759B1

    公开(公告)日：2007-08-21

    申请号：US10869698

    申请日：2004-06-16

    申请人： Kamran Zarrineh ,  Kenneth A. House ,  Syed A. Obaidulla

    发明人： Kamran Zarrineh ,  Kenneth A. House ,  Syed A. Obaidulla

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3187

    摘要： A memory BIST architecture provides an efficient communication interface between external agents, e.g., external tester and a memory BIST module. The memory BIST architecture reduces diagnostics efforts by dividing the search space and allowing the test and debug to be concentrated on the failing memory. The memory BIST architecture is divided into two levels, a memory BIST sequencer level and a satellite memory BIST module. The memory BIST sequencer level includes a set of registers that provide an interface between external agents attempting to communicate with the MBIST module and the Satellite MBIST module.

    摘要翻译： 存储器BIST架构在外部代理（例如外部测试器和存储器BIST模块）之间提供有效的通信接口。 内存BIST架构通过划分搜索空间来减少诊断工作，并允许测试和调试集中在故障存储器上。 存储器BIST架构被分为两个级别，一个存储器BIST定序器级和一个卫星存储器BIST模块。 存储器BIST定序器级别包括一组寄存器，其提供尝试与MBIST模块和卫星MBIST模块通信的外部代理之间的接口。

    Method and apparatus for testing memory cells for data retention faults
    4.
    发明授权
    Method and apparatus for testing memory cells for data retention faults 有权
    用于测试存储器单元用于数据保留故障的方法和装置

    公开(公告)号：US06681350B2

    公开(公告)日：2004-01-20

    申请号：US09681602

    申请日：2001-05-05

    申请人： R. Dean Adams ,  Aneesha P. Deo ,  Kamran Zarrineh

    发明人： R. Dean Adams ,  Aneesha P. Deo ,  Kamran Zarrineh

    IPC分类号： G11C2900

    CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/08 ,  G11C29/50016

    摘要： A method for testing memory cells for data retention faults is disclosed. A first logical value is stored in a first cell, and a second logical value is stored in a second cell of a memory device. The second cell shares the same column with the first cell. The bitlines associated with the first and second cells are prevented from being precharged before the second cell can be read. After the second cell has been read repeatedly, the first cell is read, and the bitlines associated with the first and second cells are precharged. At this point, a data retention fault is determined to have occurred if the first cell does not contain the first logical value.

    摘要翻译： 公开了一种用于测试存储器单元用于数据保持故障的方法。 第一逻辑值存储在第一单元中，第二逻辑值存储在存储器件的第二单元中。 第二个单元格与第一个单元格共享相同的列。 在第二单元可被读取之前，防止与第一和第二单元相关联的位线被预充电。 在重复读取第二单元之后，读取第一单元，并且与第一单元和第二单元相关联的位线被预充电。 此时，如果第一小区不包含第一逻辑值，则确定数据保留故障已经发生。

    Architecture of an efficient at-speed programmable memory built-in self test
    5.
    发明授权
    Architecture of an efficient at-speed programmable memory built-in self test 有权
    高效的可编程存储器的架构内置自检

    公开(公告)号：US07178076B1

    公开(公告)日：2007-02-13

    申请号：US10869720

    申请日：2004-06-16

    申请人： Kamran Zarrineh ,  Seokjin Kim

    发明人： Kamran Zarrineh ,  Seokjin Kim

    IPC分类号： G01R31/28

    CPC分类号： G11C29/16 ,  G11C2029/0401

    摘要： A method of testing an embedded memory at speed within an integrated circuit which includes providing a memory built in self test sequencer module, providing a satellite engine module coupled to the memory built in self test sequencer module and applying a march test to the embedded memory via the satellite engine module based upon information stored within the instruction buffer. The satellite engine module includes an instruction buffer and a sequence generation engine.

    摘要翻译： 一种在集成电路内以速度测试嵌入式存储器的方法，其包括提供构建在自测序列器模块中的存储器，提供耦合到内置于自测序列器模块中的存储器的卫星引擎模块，并且经由 所述卫星引擎模块基于存储在所述指令缓冲器内的信息。 卫星引擎模块包括指令缓冲器和序列生成引擎。

    Programable multi-port memory BIST with compact microcode
    6.
    发明授权
    Programable multi-port memory BIST with compact microcode 失效
    可编程多端口存储器BIST具有紧凑的微码

    公开(公告)号：US07168005B2

    公开(公告)日：2007-01-23

    申请号：US10354535

    申请日：2003-01-30

    申请人： R. Dean Adams ,  Thomas J. Eckenrode ,  Steven L. Gregor ,  Kamran Zarrineh

    发明人： R. Dean Adams ,  Thomas J. Eckenrode ,  Steven L. Gregor ,  Kamran Zarrineh

    IPC分类号： G06F11/00

    CPC分类号： G06F11/2242 ,  G11C8/16 ,  G11C29/16

    摘要： A microcode programmable built-in-self-test (BIST) circuit and method for testing a multiported memory via multiple ports, either simultaneously or sequentially, as directed by a microcode instruction word. The microcode instruction word contains a plurality of executable subinstructions and one bit of information that controls whether the test operations prescribed in the plurality of subinstructions shall be executed in parallel or in series. The executable subinstructions are dispatched by a primary controller to subcontrollers which perform test operations at each port according to the subinstructions. The microcode programable BIST architecture flexibly facilitates the testing of multiple devices, multiported devices, including multiported memory structures and complex dependent multiported memory structures. The BIST supports in-situ testing of the functionality of the memory at wafer, module, and burn-in, as well as system-level testing.

    摘要翻译： 微代码可编程内置自检（BIST）电路和方法，用于通过多个端口同时或顺序地测试多端口存储器，如微代码指令字所指示的。 微代码指令字包含多个可执行子指令和一位信息，用于控制多个子指令中规定的测试操作是并行还是串行执行。 可执行子指令由主控制器分派到根据子提示在每个端口执行测试操作的子控制器。 微码可编程BIST架构灵活地促进了多个设备，多端口设备的测试，包括多端口存储器结构和复杂的多端口存储器结构。 BIST支持在晶片，模块和老化模式下对存储器的功能进行现场测试，以及系统级测试。

    Low voltage temperature-independent and temperature-dependent voltage generator
    8.
    发明授权
    Low voltage temperature-independent and temperature-dependent voltage generator 有权
    低电压温度独立和温度依赖性电压发生器

    公开(公告)号：US06605988B1

    公开(公告)日：2003-08-12

    申请号：US10078140

    申请日：2002-02-19

    申请人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Kamran Zarrineh

    发明人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Kamran Zarrineh

    IPC分类号： G05F146

    CPC分类号： G05F3/30

    摘要： A method for using a low voltage power supply to generate a temperature-independent voltage and temperature-dependent voltage is provided. Further, an apparatus that uses a low voltage power supply to generate a temperature-independent voltage and temperature-dependent voltage is provided. The apparatus generates a temperature-dependent voltage and a temperature-independent voltage using an amplifier stage that generates a feedback signal; a startup stage that generates a startup signal dependent on the feedback signal; and an output stage that outputs the temperature-dependent voltage and the temperature-independent voltage dependent on the feedback and startup signals.

    摘要翻译： 提供一种使用低电压电源来产生与温度无关的电压和温度相关电压的方法。 此外，提供了使用低电压电源来产生与温度无关的电压和温度相关电压的装置。 该装置使用产生反馈信号的放大器级产生温度依赖电压和与温度无关的电压; 启动阶段，其根据反馈信号产生启动信号; 以及根据反馈和启动信号输出与温度有关的电压和独立于温度的电压的输出级。

    Controller for monitoring temperature
    9.
    发明授权
    Controller for monitoring temperature 有权
    用于监控温度的控制器

    公开(公告)号：US06937958B2

    公开(公告)日：2005-08-30

    申请号：US10079475

    申请日：2002-02-19

    申请人： Spencer Gold ,  Claude R. Gauthier ,  Kenneth House ,  Kamran Zarrineh

    发明人： Spencer Gold ,  Claude R. Gauthier ,  Kenneth House ,  Kamran Zarrineh

    IPC分类号： G06F1/20 ,  H01L23/34 ,  G01K1/08

    CPC分类号： G06F1/206 ,  H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A controller and method are provided for monitoring and controlling a temperature of an integrated circuit to inhibit damage from a thermal problem. The controller and method allow for individual temperature thresholds for each of one or more temperature sensors. Digital filtering of values received from temperature sensors is also provided. A variety of actions can be selected for execution upon a determination of an over-temperature condition of the integrated circuit, including assert an over-temperature pin, assert an over-temperature bit in an error register of said controller, assert an over-temperature bit in an error register of said microprocessor, issue an over-temperature interrupt to a service bus of said integrated circuit, cause a trap, slow an operating frequency of said integrated circuit, stop said integrated circuit, and do nothing.

    摘要翻译： 提供了一种控制器和方法，用于监测和控制集成电路的温度以抑制热问题的损坏。 控制器和方法允许一个或多个温度传感器中的每个温度阈值。 还提供了从温度传感器接收的值的数字滤波。 在确定集成电路的过热状态（包括断言过温引脚）时，可以选择执行各种动作，断言所述控制器的错误寄存器中的过温度位，断言过温度 位在所述微处理器的错误寄存器中，向所述集成电路的服务总线发出过温中断，引起陷阱，使所述集成电路的工作频率变慢，停止所述集成电路，并且不做任何事情。

    Automatic generation and validation of memory test models
    10.
    发明授权
    Automatic generation and validation of memory test models 有权
    内存测试模型的自动生成和验证

    公开(公告)号：US06813201B2

    公开(公告)日：2004-11-02

    申请号：US10039498

    申请日：2001-10-24

    申请人： Kamran Zarrineh ,  Thomas A. Ziaja ,  Amitava Majumdar

    发明人： Kamran Zarrineh ,  Thomas A. Ziaja ,  Amitava Majumdar

    IPC分类号： G11C700

    CPC分类号： G11C29/56004 ,  G11C29/56

    摘要： Methods and systems for automated memory test modeling generation and validation are provided. Information supplied by a graphical user interface is used to generate a customized memory primitive. The memory primitive subsequently undergoes a two phase validation to test for correct functioning.

    摘要翻译： 提供了自动内存测试建模生成和验证的方法和系统。 由图形用户界面提供的信息用于生成定制的存储器原语。 记忆基元随后进行两相验证以测试正确的功能。