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公开(公告)号：US08077063B2
公开(公告)日：2011-12-13
申请号：US12689209
申请日：2010-01-18
申请人： Ankit Pal , Girraj K. Agrawal , Asif Iqbal
发明人： Ankit Pal , Girraj K. Agrawal , Asif Iqbal
IPC分类号： H03M7/46
CPC分类号： H04L7/0331 , H03M7/46
摘要： An input bit stream is received and zone statistics such as zones count, zones center bit positions, and zones lengths are determined, where a zone is a set of non-transitioning bits in the input bit stream. Beginning and ending bit positions for each zone are determined simultaneously, and each beginning bit position is associated with an ending bit position. Zone statistics are calculated using the determined beginning and appropriate ending bit positions.
摘要翻译： 接收输入比特流并确定区域统计，诸如区域计数，区域中心比特位置和区域长度，其中区域是输入比特流中的一组非转换比特。 同时确定每个区域的开始和结束位位置，并且每个开始位位置与结束位位置相关联。 使用确定的开始和适当的结束位位置计算区域统计。
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公开(公告)号：US08432960B2
公开(公告)日：2013-04-30
申请号：US12727189
申请日：2010-03-18
申请人： Girraj K. Agrawal , Asif Iqbal , Akshat Mittal , Ankit Pal , Amrit P. Singh
发明人： Girraj K. Agrawal , Asif Iqbal , Akshat Mittal , Ankit Pal , Amrit P. Singh
IPC分类号： H03H7/30
CPC分类号： H04L25/03019 , H04L25/03885
摘要： A channel equalizer that compensates for signal distortion of a signal in a communication channel includes an equalization filter, which gain-equalizes a received signal received through the communication channel, and an equalization control circuit, which generates a gain control signal for controlling the gain of the equalization filter. The equalization control circuit specifies a phase switch in data obtained by the equalization filter as an isolated bit and generates the gain control signal based on a width of the isolated bit.
摘要翻译： 补偿通信信道中的信号的信号失真的信道均衡器包括均衡滤波器，其对通过通信信道接收的接收信号进行增益均衡，以及均衡控制电路，其产生用于控制增益的增益控制信号 均衡滤波器。 均衡控制电路指定由均衡滤波器获得的数据中的相位切换作为隔离位，并且基于隔离位的宽度生成增益控制信号。
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公开(公告)号：US08180007B2
公开(公告)日：2012-05-15
申请号：US12687844
申请日：2010-01-14
申请人： Asif Iqbal , Girraj K. Agrawal , Ankit Pal
发明人： Asif Iqbal , Girraj K. Agrawal , Ankit Pal
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： An input bit stream including a clock signal and data bits is oversampled to obtain one or more sets of data samples. One or more sets of non-transitioning phases corresponding to data samples that do not switch between zero and one are then identified. Center phases corresponding to the one or more sets of non-transitioning phases are identified and then a final center phase that accurately represents the bits belonging to the input bit stream is selected. The data samples corresponding to the final center phase are extracted, thereby recovering the clock signal and data bits from the input bit stream.
摘要翻译： 包括时钟信号和数据位的输入比特流被过采样以获得一组或多组数据采样。 然后识别对应于不在0和1之间切换的数据样本的一组或多组非转换阶段。 识别对应于一组或多组非转换阶段的中心阶段，然后选择精确地表示属于输入比特流的比特的最终中心相位。 提取对应于最终中心相位的数据样本，从而从输入比特流中恢复时钟信号和数据比特。
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公开(公告)号：US20110228839A1
公开(公告)日：2011-09-22
申请号：US12727189
申请日：2010-03-18
申请人： Girraj K. Agrawal , Asif Iqbal , Akshat Mittal , Ankit Pal , Amrit P. Singh
发明人： Girraj K. Agrawal , Asif Iqbal , Akshat Mittal , Ankit Pal , Amrit P. Singh
IPC分类号： H04L27/01
CPC分类号： H04L25/03019 , H04L25/03885
摘要： A channel equalizer that compensates for signal distortion of a signal in a communication channel includes an equalization filter, which gain-equalizes a received signal received through the communication channel, and an equalization control circuit, which generates a gain control signal for controlling the gain of the equalization filter. The equalization control circuit specifies a phase switch in data obtained by the equalization filter as an isolated bit and generates the gain control signal based on a width of the isolated bit.
摘要翻译： 补偿通信信道中的信号的信号失真的信道均衡器包括均衡滤波器，其对通过通信信道接收的接收信号进行增益均衡，以及均衡控制电路，其产生用于控制增益的增益控制信号 均衡滤波器。 均衡控制电路指定由均衡滤波器获得的数据中的相位切换作为隔离位，并且基于隔离位的宽度生成增益控制信号。
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公开(公告)号：US07986252B1
公开(公告)日：2011-07-26
申请号：US12688907
申请日：2010-01-17
申请人： Asif Iqbal , Girraj K. Agrawal , Ankit Pal
发明人： Asif Iqbal , Girraj K. Agrawal , Ankit Pal
IPC分类号： H03M13/00
CPC分类号： H03K5/1252
摘要： A bit stream is received and each bit corresponding to the bit stream is over-sampled to generate a first set of data samples. Each data sample from the first set of data samples is compared with a corresponding immediate previous data sample to generate a second set of data samples. The second set of data samples is compared with bit masks, and accordingly, some of the data samples in the first set of data samples are identified for replacement. Further, a substitute data sample is selected from the first set of data samples based on a predefined criterion and some of the data samples in the first set of data samples are replaced with the substitute data sample.
摘要翻译： 接收比特流，并且对应于比特流的每个比特被过采样以产生第一组数据样本。 将来自第一组数据样本的每个数据样本与相应的立即数据样本进行比较以生成第二组数据样本。 将第二组数据样本与位掩码进行比较，因此，第一组数据样本中的一些数据样本被识别用于替换。 此外，基于预定义的标准从第一组数据样本中选择替代数据样本，并且用替代数据样本替换第一组数据样本中的一些数据样本。
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公开(公告)号：US20110175758A1
公开(公告)日：2011-07-21
申请号：US12688907
申请日：2010-01-17
申请人： Asif Iqbal , Girraj K. Agrawal , Ankit Pal
发明人： Asif Iqbal , Girraj K. Agrawal , Ankit Pal
IPC分类号： H03M13/00
CPC分类号： H03K5/1252
摘要： A bit stream is received and each bit corresponding to the bit stream is over-sampled to generate a first set of data samples. Each data sample from the first set of data samples is compared with a corresponding immediate previous data sample to generate a second set of data samples. The second set of data samples is compared with bit masks, and accordingly, some of the data samples in the first set of data samples are identified for replacement. Further, a substitute data sample is selected from the first set of data samples based on a predefined criterion and some of the data samples in the first set of data samples are replaced with the substitute data sample.
摘要翻译： 接收比特流，并且对应于比特流的每个比特被过采样以产生第一组数据样本。 将来自第一组数据样本的每个数据样本与相应的立即数据样本进行比较以生成第二组数据样本。 将第二组数据样本与位掩码进行比较，因此，第一组数据样本中的一些数据样本被识别用于替换。 此外，基于预定义的标准从第一组数据样本中选择替代数据样本，并且用替代数据样本替换第一组数据样本中的一些数据样本。
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公开(公告)号：US20110170644A1
公开(公告)日：2011-07-14
申请号：US12687844
申请日：2010-01-14
申请人： Asif IQBAL , Girraj K. Agrawal , Ankit Pal
发明人： Asif IQBAL , Girraj K. Agrawal , Ankit Pal
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： An input bit stream including a clock signal and data bits is oversampled to obtain one or more sets of data samples. One or more sets of non-transitioning phases corresponding to data samples that do not switch between zero and one are then identified. Center phases corresponding to the one or more sets of non-transitioning phases are identified and then a final center phase that accurately represents the bits belonging to the input bit stream is selected. The data samples corresponding to the final center phase are extracted, thereby recovering the clock signal and data bits from the input bit stream.
摘要翻译： 包括时钟信号和数据位的输入比特流被过采样以获得一组或多组数据采样。 然后识别对应于不在0和1之间切换的数据样本的一组或多组非转换阶段。 识别对应于一组或多组非转换阶段的中心阶段，然后选择精确地表示属于输入比特流的比特的最终中心相位。 提取对应于最终中心相位的数据样本，从而从输入比特流中恢复时钟信号和数据比特。
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公开(公告)号：US09158921B1
公开(公告)日：2015-10-13
申请号：US14274770
申请日：2014-05-12
CPC分类号： G06F21/575 , G06F1/32 , G06F1/3275 , G06F21/64
摘要： A processing system has a stored, encrypted data structure that is decrypted to provide verification data values. System data values are retrieved from locations distributed about a memory storing system data. The verification data values are compared with corresponding system data values to determine if a predetermined threshold of verification data values matches the system data values. The system resumes operation if the predetermined threshold is met.
摘要翻译： 处理系统具有被解密以提供验证数据值的存储的加密数据结构。 从分布在存储系统数据的存储器的位置检索系统数据值。 将验证数据值与对应的系统数据值进行比较，以确定验证数据值的预定阈值是否与系统数据值匹配。 如果满足预定阈值，则系统恢复运行。
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公开(公告)号：US20150288366A1
公开(公告)日：2015-10-08
申请号：US14248332
申请日：2014-04-08
申请人： Amit Aggarwal , Himanshu Goel , Ashish Malhotra , Ankit Pal
发明人： Amit Aggarwal , Himanshu Goel , Ashish Malhotra , Ankit Pal
摘要： An integrated circuit (IC) includes multiple circuit modules that have specific clocking requirements, multiple clock sources (e.g., PLLs, duty cycle re-shaper, etc.), and at least one clock input port. The clock sources have specific clock source specifications, and the circuit modules have specific clocking requirements. The clock sources are selected based on an identification of the most common clocking requirements, and then placed at routing distances measured from the input port that are less than corresponding predetermined maximum routing distances such that the clocking requirements of the circuit modules are met. The IC thus generates clock signals internally, rather than externally.
摘要翻译： 集成电路（IC）包括具有特定时钟要求的多个电路模块，多个时钟源（例如，PLL，占空比重新整形器等）以及至少一个时钟输入端口。 时钟源具有特定的时钟源规格，电路模块具有特定的时钟要求。 基于最常见的时钟要求的识别来选择时钟源，然后将其从输入端口测量的路由距离设置为小于相应的预定最大路由距离，使得满足电路模块的时钟要求。 因此，IC在内部而不是外部产生时钟信号。
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公开(公告)号：US20150309803A1
公开(公告)日：2015-10-29
申请号：US14261407
申请日：2014-04-24
申请人： Priti Sahu , Poonam Aggrwal , Prabhakar Kushwaha , Ankit Pal
发明人： Priti Sahu , Poonam Aggrwal , Prabhakar Kushwaha , Ankit Pal
CPC分类号： G06F11/1417 , G06F9/4401 , G06F9/4403 , G06F11/1666
摘要： A fail-safe booting system suitable for a system-on-chip (SOC) automatically detects and rectifies failures in power-on reset (POR) configuration or boot loader fetch operations. If a failure due to a boot loader fetch occurs, a POR configuration and boot loader are fetched from a different non-volatile memory. The reloading takes place from further different non-volatile memory sources if the boot loader fetch fails again. The automated system operates in accordance with a state machine, and does not involve any manual, on-board switch selection or manual re-programming.
摘要翻译： 适用于片上系统（SOC）的故障安全引导系统自动检测并纠正上电复位（POR）配置或引导加载程序提取操作中的故障。 如果由于引导加载程序提取而导致故障，则从不同的非易失性内存中提取POR配置和引导加载程序。 如果引导加载程序提取再次失败，则会从更多不同的非易失性内存源进行重新加载。 自动化系统根据状态机进行操作，不涉及手动，车载开关选择或手动重新编程。
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