-
公开(公告)号：US08406078B2
公开(公告)日：2013-03-26
申请号：US13025668
申请日：2011-02-11
申请人： Annie Lum , Derek C. Tao , Young Seog Kim
发明人： Annie Lum , Derek C. Tao , Young Seog Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/12 , G11C5/147 , G11C11/412 , G11C11/413
摘要： A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers.
摘要翻译： 存储电路包括以列方式设置的第一多个存储器阵列。 存储器电路包括第一多个保持器，每个保持器与第一多个存储器阵列中的对应的一个存储器阵列电耦合。 第一限流器与第一多个保持器电耦合并共享。 第一多个扇区开关各自在第一限流器和第一多个保持器中的相应一个之间电耦合。
-
公开(公告)号：US08519444B2
公开(公告)日：2013-08-27
申请号：US12879447
申请日：2010-09-10
申请人： Annie Lum , Derek C. Tao , Cheng Hung Lee , Chung-Ji Lu , Hong-Chen Cheng , Vineet Kumar Agrawal , Keun-Young Kim , Pyong Yun Cho
发明人： Annie Lum , Derek C. Tao , Cheng Hung Lee , Chung-Ji Lu , Hong-Chen Cheng , Vineet Kumar Agrawal , Keun-Young Kim , Pyong Yun Cho
IPC分类号： H01L27/118
CPC分类号： G06F17/5068 , G06F17/5081 , G06F2217/12 , H01L27/0207 , H01L27/088 , Y02P90/265
摘要： The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.
摘要翻译： 上述布局，装置结构和方法利用虚设装置将边缘结构和/或非允许结构的扩散区域扩展到虚设装置。 这种扩散区域的扩展可解决或减少LOD和边缘效应问题。 此外，在边缘装置旁边处理伪装置的栅极结构也仅允许在虚设装置旁边添加一个虚拟结构，并将该不动产保存在半导体芯片上。 虚拟设备被禁用，其性能不重要。 因此，利用虚设装置根据设计规则扩展边缘结构和/或非允许结构的扩散区域允许分辨率或降低或LOD和边缘效应发生，而不会降低成品率或增加布局面积。
-
公开(公告)号：US08395960B2
公开(公告)日：2013-03-12
申请号：US12778714
申请日：2010-05-12
IPC分类号： G11C8/00
CPC分类号： G11C5/147 , G11C11/412 , G11C11/413
摘要： A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers.
摘要翻译： 存储电路包括以列方式设置的第一多个存储器阵列。 存储器电路包括第一多个保持器，每个保持器与第一多个存储器阵列中的对应的一个存储器阵列电耦合。 第一限流器与第一多个保持器电耦合并共享。
-
公开(公告)号：US07782692B2
公开(公告)日：2010-08-24
申请号：US11971901
申请日：2008-01-09
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/18 , G11C2207/002
摘要： A read module for register files includes at least one local I/O module coupled to a memory cell for outputting a value stored in the memory cell; and at least one global bit line driver having an input terminal coupled to the local I/O module, and a output terminal coupled to a global bit line for selectively pre-charging the global bit line at a default voltage in response to a local pre-charge signal, and outputting the value stored in the memory cell to the global bit line when the local pre-charge signal is not asserted.
摘要翻译： 用于寄存器文件的读取模块包括耦合到存储器单元的至少一个本地I / O模块，用于输出存储在存储单元中的值; 以及具有耦合到本地I / O模块的输入端的至少一个全局位线驱动器，以及耦合到全局位线的输出端，用于响应于本地预置位选择性地以默认电压对全局位线预充电 并且当本地预充电信号未被置位时，将存储在存储单元中的值输出到全局位线。
-
公开(公告)号：US20090175099A1
公开(公告)日：2009-07-09
申请号：US11971901
申请日：2008-01-09
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/18 , G11C2207/002
摘要： A read module for register files includes at least one local I/O module coupled to a memory cell for outputting a value stored in the memory cell; and at least one global bit line driver having an input terminal coupled to the local I/O module, and a output terminal coupled to a global bit line for selectively pre-charging the global bit line at a default voltage in response to a local pre-charge signal, and outputting the value stored in the memory cell to the global bit line when the local pre-charge signal is not asserted.
摘要翻译： 用于寄存器文件的读取模块包括耦合到存储器单元的至少一个本地I / O模块，用于输出存储在存储器单元中的值; 以及具有耦合到本地I / O模块的输入端的至少一个全局位线驱动器，以及耦合到全局位线的输出端，用于响应于本地预置位选择性地以默认电压对全局位线预充电 并且当本地预充电信号未被置位时，将存储在存储单元中的值输出到全局位线。
-
-
-
-
搜索结果
5 条记录 (耗时 0.019 秒)
