-
公开(公告)号：US08665592B2
公开(公告)日：2014-03-04
申请号：US13280864
申请日：2011-10-25
CPC分类号： G06F1/206 , G06F2200/201 , Y02D10/16
摘要： A multi-core microprocessor provides an indication of the power management state of each of the cores on output terminals. Cooling of the cores is adjusted responsive to the indication of the power management state of the respective cores with additional cooling being provided to those cores in a more active state and less cooling provided to those cores in a less active state.
摘要翻译： 多核微处理器提供输出端子上每个核心的功率管理状态的指示。 响应于各个核心的功率管理状态的指示来响应于各个核心的功率管理状态的指示来调节内核的冷却，其中在处于更活跃状态的情况下向这些核心提供额外的冷却，并且在较不活跃状态下提供给那些核心的冷却
-
公开(公告)号：US20120039041A1
公开(公告)日：2012-02-16
申请号：US13280864
申请日：2011-10-25
CPC分类号： G06F1/206 , G06F2200/201 , Y02D10/16
摘要： A multi-core microprocessor provides an indication of the power management state of each of the cores on output terminals. Cooling of the cores is adjusted responsive to the indication of the power management state of the respective cores with additional cooling being provided to those cores in a more active state and less cooling provided to those cores in a less active state.
摘要翻译： 多核微处理器提供输出端子上每个核心的功率管理状态的指示。 响应于各个核心的功率管理状态的指示来响应于各个核心的功率管理状态的指示来调节内核的冷却，其中在处于更活跃状态的情况下向这些核心提供额外的冷却，并且在较不活跃状态下提供给那些核心的冷却
-
公开(公告)号：US08064197B2
公开(公告)日：2011-11-22
申请号：US12470956
申请日：2009-05-22
CPC分类号： G06F1/206 , G06F2200/201 , Y02D10/16
摘要： A multi-core microprocessor provides an indication of the power management state of each of the cores on output terminals. Cooling of the cores is adjusted responsive to the indication of the power management state of the respective cores with additional cooling being provided to those cores in a more active state and less cooling provided to those cores in a less active state.
摘要翻译： 多核微处理器提供输出端子上每个核心的功率管理状态的指示。 响应于各个核心的功率管理状态的指示来响应于各个核心的功率管理状态的指示来调节内核的冷却，其中在处于更活跃状态的情况下向这些核心提供额外的冷却，并且在较不活跃状态下提供给那些核心的冷却
-
公开(公告)号：US20100296238A1
公开(公告)日：2010-11-25
申请号：US12470956
申请日：2009-05-22
IPC分类号： H05K7/20
CPC分类号： G06F1/206 , G06F2200/201 , Y02D10/16
摘要： A multi-core microprocessor provides an indication of the power management state of each of the cores on output terminals. Cooling of the cores is adjusted responsive to the indication of the power management state of the respective cores with additional cooling being provided to those cores in a more active state and less cooling provided to those cores in a less active state.
摘要翻译： 多核微处理器提供输出端子上每个核心的功率管理状态的指示。 响应于各个核心的功率管理状态的指示来响应于各个核心的功率管理状态的指示来调节内核的冷却，其中在处于更活跃状态的情况下向这些核心提供额外的冷却，并且在较不活跃状态下提供给那些核心的冷却
-
5.发明申请METHOD OF OPTIMIZING SIDEWALL SPACER SIZE FOR SILICIDE PROXIMITY WITH IN-SITU CLEAN 有权利用现场清洁优化硅酸盐污染物尺寸的方法公开(公告)号：US20090286389A1
公开(公告)日：2009-11-19
申请号：US12122840
申请日：2008-05-19
申请人： David G. Farber , Fred Hause , Markus Lenski , Anthony C. Mowry
发明人： David G. Farber , Fred Hause , Markus Lenski , Anthony C. Mowry
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/665 , H01L21/28052 , H01L29/6653 , H01L29/78
摘要： A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.
摘要翻译： 一种方法，包括在衬底上形成半导体器件的栅极，并且蚀刻栅极侧面上的侧壁间隔物以提供接近值，其中接近值被定义为栅极与性能增强的边缘之间的距离 地区。 侧壁间隔件用于在衬底中形成区域期间限定区域的边缘。 该方法还包括预先清洁栅极和基板以准备形成区域，其中在连续真空中进行蚀刻和预清洁。
-
公开(公告)号：US07741663B2
公开(公告)日：2010-06-22
申请号：US12258188
申请日：2008-10-24
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/6659 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/7833 , Y10S257/90
摘要： Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic “miller” capacitance.
摘要翻译： 小型化的复合晶体管器件形成有减少的泄漏和减小的磨机电容。 实施例包括通过利用低K介电常数侧壁间隔物材料在栅电极和源极/漏极接触之间具有减小的电容的晶体管。 一个实施例包括在半导体衬底上形成栅电极，在栅电极的侧表面上形成侧壁间隔物，通过离子注入形成源/漏区，在栅电极，侧壁间隔物和衬底上形成层间电介质，以及 通过层间电介质形成源极/漏极接触。 然后去除侧壁间隔物和层间电介质。 然后将诸如低K电介质材料的电介质材料沉积在栅电极和源极/漏极接触之间的间隙中，从而形成气隙，由此减小寄生“铣”电容。
-
公开(公告)号：US20100102363A1
公开(公告)日：2010-04-29
申请号：US12258188
申请日：2008-10-24
IPC分类号： H01L47/00 , H01L21/336
CPC分类号： H01L29/6659 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/7833 , Y10S257/90
摘要： Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic “miller” capacitance.
摘要翻译： 小型化的复合晶体管器件形成有减少的泄漏和减小的磨机电容。 实施例包括通过利用低K介电常数侧壁间隔物材料在栅电极和源极/漏极接触之间具有减小的电容的晶体管。 一个实施例包括在半导体衬底上形成栅电极，在栅电极的侧表面上形成侧壁间隔物，通过离子注入形成源/漏区，在栅电极，侧壁间隔物和衬底上形成层间电介质，以及 通过层间电介质形成源/漏接触。 然后去除侧壁间隔物和层间电介质。 然后将诸如低K电介质材料的电介质材料沉积在栅电极和源极/漏极接触之间的间隙中，从而形成气隙，由此减小寄生“铣”电容。
-
8.发明授权Method of optimizing sidewall spacer size for silicide proximity with in-situ clean 有权用于原位清洁优化硅化物接近的侧壁间隔尺寸的方法公开(公告)号：US07745337B2
公开(公告)日：2010-06-29
申请号：US12122840
申请日：2008-05-19
申请人： David G. Farber , Fred Hause , Markus Lenski , Anthony C. Mowry
发明人： David G. Farber , Fred Hause , Markus Lenski , Anthony C. Mowry
IPC分类号： H01L21/311
CPC分类号： H01L29/665 , H01L21/28052 , H01L29/6653 , H01L29/78
摘要： A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.
摘要翻译： 一种方法，包括在衬底上形成半导体器件的栅极，并且蚀刻栅极侧面上的侧壁间隔物以提供接近值，其中接近值被定义为栅极与性能增强的边缘之间的距离 地区。 侧壁间隔件用于在衬底中形成区域期间限定区域的边缘。 该方法还包括预先清洁栅极和基板以准备形成区域，其中在连续真空中进行蚀刻和预清洁。
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.024 秒)