公开(公告)号：US5783340A

公开(公告)日：1998-07-21

申请号：US903985

申请日：1997-07-31

申请人： Anthony J. Farino ,  Stephen Montague ,  Jeffry J. Sniegowski ,  James H. Smith ,  Paul J. McWhorter

发明人： Anthony J. Farino ,  Stephen Montague ,  Jeffry J. Sniegowski ,  James H. Smith ,  Paul J. McWhorter

IPC分类号： B81B3/00 ,  B81B7/00 ,  B81B7/02 ,  G03F7/09 ,  G03F7/207 ,  G03F9/00 ,  G01B11/00

CPC分类号： G03F7/094 ,  B81C1/00246 ,  G03F9/70 ,  B81C2203/0728 ,  G01P2015/0828

摘要： A method is disclosed for photolithographically defining device features up to the resolution limit of an auto-focusing projection stepper when the device features are to be formed in a wafer cavity at a depth exceeding the depth of focus of the stepper. The method uses a focusing cavity located in a die field at the position of a focusing light beam from the auto-focusing projection stepper, with the focusing cavity being of the same depth as one or more adjacent cavities wherein a semiconductor device is to be formed. The focusing cavity provides a bottom surface for referencing the focusing light beam and focusing the stepper at a predetermined depth below the surface of the wafer, whereat the device features are to be defined. As material layers are deposited in each device cavity to build up a semiconductor structure such as a microelectromechanical system (MEMS) device, the same material layers are deposited in the focusing cavity, raising the bottom surface and re-focusing the stepper for accurately defining additional device features in each succeeding material layer. The method is especially applicable for forming MEMS devices within a cavity or trench and integrating the MEMS devices with electronic circuitry fabricated on the wafer surface.

摘要翻译： 公开了一种用于光刻地限定器件特征的方法，直到在超过步进器的焦深深度的晶片腔中形成器件特征时，自动聚焦投影步进器的分辨率极限。 该方法使用位于来自自动聚焦投影步进机的聚焦光束的位置处的模场中的聚焦腔，其中聚焦腔具有与一个或多个相邻空腔相同的深度，其中将形成半导体器件 。 聚焦腔提供用于参考聚焦光束的底表面，并将步进器聚焦在晶片表面下方的预定深度处，其中将限定器件特征。 当材料层沉积在每个器件腔中以建立诸如微机电系统（MEMS）器件的半导体结构时，相同的材料层沉积在聚焦腔中，提高底表面并重新聚焦步进器以准确地限定附加的 每个后续材料层中的器件特征。 该方法特别适用于在腔或沟槽内形成MEMS器件，并将MEMS器件与在晶片表面上制造的电子电路集成。

公开(公告)号：US06682607B1

公开(公告)日：2004-01-27

申请号：US10092215

申请日：2002-03-05

申请人： Anthony J. Farino

发明人： Anthony J. Farino

IPC分类号： B08B304

CPC分类号： H01L21/31133 ,  B08B3/02 ,  G03F7/3021 ,  G03F7/422 ,  H01L21/67028 ,  H01L21/6708 ,  Y10S134/902

摘要： A method for reconditioning the surface of a semiconductor substrate to remove an unwanted (i.e. defective) layer of photoresist is disclosed. The method adapts a conventional automated spinner which is used to rotate the substrate at high speed while a stream of a first solvent (e.g. acetone) is used to dissolve the photoresist. A stream of a second solvent (e.g. methanol) is then used to clean the substrate at a lower speed, with the substrate being allowed to dry with continued rotation. The method of the present invention can be used within a photolithography track so that the substrates need never leave the track for reconditioning.

摘要翻译： 公开了一种用于修复半导体衬底的表面以去除不需要的（即有缺陷的）光致抗蚀剂层的方法。 该方法适用于常规的自动旋转器，其用于以高速旋转基底，同时使用第一溶剂（例如丙酮）流来溶解光致抗蚀剂。 然后使用第二溶剂（例如甲醇）的流以更低的速度清洗基材，使基材持续旋转干燥。 本发明的方法可以在光刻轨道内使用，使得基板不需要离开轨道进行修复。

公开(公告)号：US08575748B1

公开(公告)日：2013-11-05

申请号：US13324076

申请日：2011-12-13

申请人： Anthony J. Farino

发明人： Anthony J. Farino

IPC分类号： H01L23/12

CPC分类号： H01L23/10 ,  B81B2201/0271 ,  B81C1/00269 ,  B81C1/00825 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

摘要翻译： 可以通过将设置在第一半导体晶片的第一表面上的密封环与设置在第二半导体晶片的第二表面上的密封环相对的关系对准设置在密封封装中，并且围绕第二半导体晶片的一部分 包含设备的晶圆。 第一和第二晶片表面朝向彼此的强制移动将第一和第二密封环彼此压缩。 在第一和第二晶片表面之间提供了除第一和第二密封环之外的运动的物理屏障。