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公开(公告)号：US20130009227A1
公开(公告)日：2013-01-10
申请号：US13614479
申请日：2012-09-13
IPC分类号： H01L27/07 , H01L21/8234
CPC分类号： H01L27/0808 , H01L21/26513 , H01L27/0811 , H01L27/088 , H01L29/7836
摘要： A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.
摘要翻译： 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底，场效应晶体管结构，其包括源区，第一体区，漏区，栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构，其包括栅极 - 漏极电容，该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值，或者在给定的反向电压下包括平台状过程。
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公开(公告)号：US20100025748A1
公开(公告)日：2010-02-04
申请号：US12184819
申请日：2008-08-01
IPC分类号： H01L29/94 , H01L21/8234
CPC分类号： H01L27/0808 , H01L21/26513 , H01L27/0811 , H01L27/088 , H01L29/7836
摘要： A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.
摘要翻译： 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底，场效应晶体管结构，其包括源区，第一体区，漏区，栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构，其包括栅极 - 漏极电容，该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值，或者在给定的反向电压下包括平台状过程。
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公开(公告)号：US08829584B2
公开(公告)日：2014-09-09
申请号：US13614479
申请日：2012-09-13
IPC分类号： H01L27/07
CPC分类号： H01L27/0808 , H01L21/26513 , H01L27/0811 , H01L27/088 , H01L29/7836
摘要： A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.
摘要翻译： 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底，场效应晶体管结构，其包括源区，第一体区，漏区，栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构，其包括栅极 - 漏极电容，该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值，或者在给定的反向电压下包括平台状过程。
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公开(公告)号：US08273622B2
公开(公告)日：2012-09-25
申请号：US13161050
申请日：2011-06-15
IPC分类号： H01L29/94
CPC分类号： H01L27/0808 , H01L21/26513 , H01L27/0811 , H01L27/088 , H01L29/7836
摘要： A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.
摘要翻译： 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底，场效应晶体管结构，其包括源区，第一体区，漏区，栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构，其包括栅极 - 漏极电容，该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值，或者在给定的反向电压下包括平台状过程。
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公开(公告)号：US20110244646A1
公开(公告)日：2011-10-06
申请号：US13161050
申请日：2011-06-15
IPC分类号： H01L21/336
CPC分类号： H01L27/0808 , H01L21/26513 , H01L27/0811 , H01L27/088 , H01L29/7836
摘要： A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.
摘要翻译： 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底，场效应晶体管结构，其包括源区，第一体区，漏区，栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构，其包括栅极 - 漏极电容，该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值，或者在给定的反向电压下包括平台状过程。
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公开(公告)号：US07982253B2
公开(公告)日：2011-07-19
申请号：US12184819
申请日：2008-08-01
IPC分类号： H01L29/94
CPC分类号： H01L27/0808 , H01L21/26513 , H01L27/0811 , H01L27/088 , H01L29/7836
摘要： A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.
摘要翻译： 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底，场效应晶体管结构，其包括源区，第一体区，漏区，栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构，其包括栅极 - 漏极电容，该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地改变。 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值，或者在给定的反向电压下包括平台状过程。
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7.发明授权Semiconductor device having additional capacitance to inherent gate-drain or inherent drain-source capacitance 有权具有对固有栅极漏极或固有漏极 - 源极电容的附加电容的半导体器件公开(公告)号：US07977737B2
公开(公告)日：2011-07-12
申请号：US12043429
申请日：2008-03-06
申请人： Armin Willmeroth , Winfried Kaindl , Carolin Tolksdorf , Anton Mauder , Holger Kapels , Gerald Deboy , Franz Hirler
发明人： Armin Willmeroth , Winfried Kaindl , Carolin Tolksdorf , Anton Mauder , Holger Kapels , Gerald Deboy , Franz Hirler
IPC分类号： H01L29/66 , H01L21/337
CPC分类号： H01L27/0733 , H01L2224/48091 , H01L2224/4813 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device with inherent capacitances and method for its production. The semiconductor device has an inherent feedback capacitance between a control electrode and a first electrode. In addition, the semiconductor device has an inherent drain-source capacitance between the first electrode and a second electrode. At least one monolithically integrated additional capacitance is connected in parallel to the inherent feedback capacitance or in parallel to the inherent drain-source capacitance. The additional capacitance comprises a first capacitor surface and a second capacitor surface opposite the first capacitor surface. The capacitor surfaces are structured conductive layers of the semiconductor device on a front side of the semiconductor body, between which a dielectric layer is located and which form at least one additional capacitor.
摘要翻译： 具有固有电容的半导体器件及其制造方法。 半导体器件在控制电极和第一电极之间具有固有的反馈电容。 此外，半导体器件在第一电极和第二电极之间具有固有的漏极 - 源极电容。 至少一个单片集成附加电容与固有反馈电容并联连接，或与固有漏 - 源电容并联连接。 附加电容包括与第一电容器表面相对的第一电容器表面和第二电容器表面。 电容器表面是半导体器件的前侧上的半导体器件的结构化导电层，介电层位于其之间，并形成至少一个附加电容器。
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8.发明申请公开(公告)号：US20090224302A1
公开(公告)日：2009-09-10
申请号：US12043429
申请日：2008-03-06
申请人： Armin Willmeroth , Winfried Kaindl , Carolin Tolksdorf , Anton Mauder , Holger Kapels , Gerald Deboy , Franz Hirler
发明人： Armin Willmeroth , Winfried Kaindl , Carolin Tolksdorf , Anton Mauder , Holger Kapels , Gerald Deboy , Franz Hirler
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L27/0733 , H01L2224/48091 , H01L2224/4813 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device with inherent capacitances and method for its production. The semiconductor device has an inherent feedback capacitance between a control electrode and a first electrode. In addition, the semiconductor device has an inherent drain-source capacitance between the first electrode and a second electrode. At least one monolithically integrated additional capacitance is connected in parallel to the inherent feedback capacitance or in parallel to the inherent drain-source capacitance. The additional capacitance comprises a first capacitor surface and a second capacitor surface opposite the first capacitor surface. The capacitor surfaces are structured conductive layers of the semiconductor device on a front side of the semiconductor body, between which a dielectric layer is located and which form at least one additional capacitor.
摘要翻译： 具有固有电容的半导体器件及其制造方法。 半导体器件在控制电极和第一电极之间具有固有的反馈电容。 此外，半导体器件在第一电极和第二电极之间具有固有的漏极 - 源极电容。 至少一个单片集成附加电容与固有反馈电容并联连接，或与固有漏 - 源电容并联连接。 附加电容包括与第一电容器表面相对的第一电容器表面和第二电容器表面。 电容器表面是半导体器件的前侧上的半导体器件的结构化导电层，介电层位于其之间，并形成至少一个附加电容器。
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公开(公告)号：US08294206B2
公开(公告)日：2012-10-23
申请号：US13161130
申请日：2011-06-15
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0839 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/7396
摘要： An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an insulating layer controls channel regions of body zones for a current flow between the two electrodes. A drift section adjoining the channel regions comprises drift zones and charge compensation zones. A part of the charge compensation zones includes conductively connected charge compensation zones electrically connected to the first electrode. Another part includes nearly-floating charge compensation zones, so that an increased control electrode surface has a monolithically integrated additional capacitance CZGD in a cell region of the semiconductor device.
摘要翻译： 集成电路器件包括在相对表面上装配有第一电极和第二电极的半导体本体。 绝缘层上的控制电极控制两个电极之间电流的体区的通道区域。 与沟道区相邻的漂移区包括漂移区和电荷补偿区。 电荷补偿区域的一部分包括与第一电极电连接的导电连接的电荷补偿区。 另一部分包括几乎浮动的电荷补偿区，使得增加的控制电极表面在半导体器件的单元区域中具有单片集成的附加电容CZGD。
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公开(公告)号：US20110241104A1
公开(公告)日：2011-10-06
申请号：US13161130
申请日：2011-06-15
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0839 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/7396
摘要： An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an insulating layer controls channel regions of body zones for a current flow between the two electrodes. A drift section adjoining the channel regions comprises drift zones and charge compensation zones. A part of the charge compensation zones includes conductively connected charge compensation zones electrically connected to the first electrode. Another part includes nearly-floating charge compensation zones, so that an increased control electrode surface has a monolithically integrated additional capacitance CZGD in a cell region of the semiconductor device.
摘要翻译： 集成电路器件包括在相对表面上装配有第一电极和第二电极的半导体本体。 绝缘层上的控制电极控制两个电极之间电流的体区的通道区域。 与沟道区相邻的漂移区包括漂移区和电荷补偿区。 电荷补偿区域的一部分包括与第一电极电连接的导电连接的电荷补偿区。 另一部分包括几乎浮动的电荷补偿区，使得增加的控制电极表面在半导体器件的单元区域中具有单片集成的附加电容CZGD。
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