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1.发明授权公开(公告)号：US07576591B2
公开(公告)日：2009-08-18
申请号：US11780206
申请日：2007-07-19
申请人： Antonino Conte , Carmelo Ucciardello , Carmine D'Alessandro , Mario Micciche , Giovanni Matranga , Diego De Costantini
发明人： Antonino Conte , Carmelo Ucciardello , Carmine D'Alessandro , Mario Micciche , Giovanni Matranga , Diego De Costantini
IPC分类号： G05F1/10
摘要： A charge pump system is provided that includes at least one first pump for generating a first working voltage, a second pump for generating a second working voltage, and a third pump for generating a third working voltage. The first pump is connected to an internal supply voltage reference that can having a limited value, and has an output terminal connected to the second and third pumps so as to supplying them with the first working voltage as their supply voltage. A method is also provided for managing the generation of voltages to be used with such a charge pump system.
摘要翻译： 提供一种电荷泵系统，其包括用于产生第一工作电压的至少一个第一泵，用于产生第二工作电压的第二泵和用于产生第三工作电压的第三泵。 第一泵连接到可以具有有限值的内部电源参考电压，并且具有连接到第二和第三泵的输出端，以便向它们提供第一工作电压作为它们的电源电压。 还提供了一种用于管理与这种电荷泵系统一起使用的电压的产生的方法。
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2.发明授权Dynamic biasing circuit for a protection stage using low voltage transistors 有权用于使用低压晶体管的保护级的动态偏置电路公开(公告)号：US08604868B2
公开(公告)日：2013-12-10
申请号：US13435210
申请日：2012-03-30
IPC分类号： G05F1/10
CPC分类号： H03K17/102 , H03K3/356113
摘要： A biasing circuit may include an input configured to receive a supply voltage, a value of which is higher than a limit voltage. The biasing circuit may also include a control stage configured to generate first and second control signals with mutually complementary values, equal alternatively to a first value, in a first half-period of a clock signal, or to a second value, in a second half-period of the clock signal. The first and second values may be a function of the supply and limit voltages. The biasing circuit may also include a biasing stage configured to generate a biasing voltage as a function of the values of the first and second control signals. The first and second control signals may control transfer transistors for transferring the supply voltage to respective outputs, while the biasing voltage may be for controlling protection transistors to reduce overvoltages on the transfer transistors.
摘要翻译： 偏置电路可以包括被配置为接收其值高于限制电压的电源电压的输入。 偏置电路还可以包括控制级，其被配置为在时钟信号的第一半个周期中产生第二和第二控制信号，该第一和第二控制信号具有相互互补的值，等于第一个值，或在第二个半个时钟信号中的第二个值 时钟信号的周期。 第一和第二值可以是电源和极限电压的函数。 偏置电路还可以包括被配置为产生作为第一和第二控制信号的值的函数的偏置电压的偏置级。 第一和第二控制信号可以控制用于将电源电压传送到各个输出的转移晶体管，而偏置电压可以用于控制保护晶体管以减小转移晶体管的过电压。
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3.发明申请ELECTRONIC CIRCUIT FOR GENERATING LOW VOLTAGE AND HIGH FREQUENCY PHASES IN A CHARGE PUMP 有权用于在充电泵中产生低电压和高频相位的电子电路公开(公告)号：US20100127760A1
公开(公告)日：2010-05-27
申请号：US12559967
申请日：2009-09-15
IPC分类号： G05F3/02
CPC分类号： H02M3/073 , H02M2003/077
摘要： A charge pump latch circuit is provided that includes at least one first and at least one second charge pump stage interconnected by an intermediate circuit node, and a stabilization stage connected to the intermediate circuit node and to control terminals of transistors of the first and second charge pump stages. The stabilization stage includes at least one first pair and at least one second pair of first and second enable terminals receiving suitable and distinct phase signals that ensure the turn-off of the stabilization stage during overlapping periods of the phase signals. Also provided is a method for using a stabilization stage to drive transistors in first and second charge pump stages that are interconnected by an intermediate circuit node.
摘要翻译： 提供一种电荷泵锁存电路，其包括由中间电路节点互连的至少一个第一和至少一个第二电荷泵级，以及连接到中间电路节点的稳定级，并且控制第一和第二电荷的晶体管的端子 泵级。 稳定级包括至少一个第一对和至少一个第二对第一和第二使能端，其接收合适且不同的相位信号，以确保在相位信号的重叠周期期间稳定级的关断。 还提供了一种使用稳定级来驱动由中间电路节点互连的第一和第二电荷泵级中的晶体管的方法。
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4.发明授权Electronic circuit for generating low voltage and high frequency phases in a charge pump 有权用于在电荷泵中产生低电压和高频相的电子电路公开(公告)号：US08063693B2
公开(公告)日：2011-11-22
申请号：US12559967
申请日：2009-09-15
CPC分类号： H02M3/073 , H02M2003/077
摘要： A charge pump latch circuit is provided that includes at least one first and at least one second charge pump stage interconnected by an intermediate circuit node, and a stabilization stage connected to the intermediate circuit node and to control terminals of transistors of the first and second charge pump stages. The stabilization stage includes at least one first pair and at least one second pair of first and second enable terminals receiving suitable and distinct phase signals that ensure the turn-off of the stabilization stage during overlapping periods of the phase signals. Also provided is a method for using a stabilization stage to drive transistors in first and second charge pump stages that are interconnected by an intermediate circuit node.
摘要翻译： 提供一种电荷泵锁存电路，其包括由中间电路节点互连的至少一个第一和至少一个第二电荷泵级，以及连接到中间电路节点的稳定级，并且控制第一和第二电荷的晶体管的端子 泵级。 稳定级包括至少一个第一对和至少一个第二对第一和第二使能端，其接收合适且不同的相位信号，以确保在相位信号的重叠周期期间稳定级的关断。 还提供了一种使用稳定级来驱动由中间电路节点互连的第一和第二电荷泵级中的晶体管的方法。
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公开(公告)号：US20080101125A1
公开(公告)日：2008-05-01
申请号：US11977876
申请日：2007-10-26
申请人： Antonino Conte , Gianbattista Logiudice , Giovanni Matranga , Mario Micciche' , Carmelo Ucciardello , Diego De Costantini
发明人： Antonino Conte , Gianbattista Logiudice , Giovanni Matranga , Mario Micciche' , Carmelo Ucciardello , Diego De Costantini
IPC分类号： G11C16/04
CPC分类号： G11C16/12
摘要： An EEPROM memory having a matrix of individually selectable memory cells, the matrix having a plurality of columns, a plurality of data lines each coupled with the cells of a corresponding column, the data lines being grouped in a plurality of packets, a plurality of biasing elements for providing a biasing signal to the data lines, and means for selecting the biasing elements for a selected one of the packets, wherein each biasing element is associated with corresponding data lines of a plurality of packets, the biasing element comprising switching means for selectively applying the biasing signal to a selected one of the associated data lines.
摘要翻译： 一种EEPROM存储器，具有单独可选择的存储单元矩阵，该矩阵具有多个列，多个数据线，每条数据线与相应列的单元相耦合，数据线被分组成多个分组，多个偏置 用于向数据线提供偏置信号的元件以及用于为所选分组中的所选择的一个分组选择偏置元件的装置，其中每个偏置元件与多个分组的相应数据线相关联，所述偏置元件包括用于选择性地 将偏置信号应用到所选择的一个相关联的数据线。
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6.发明申请公开(公告)号：US20120274393A1
公开(公告)日：2012-11-01
申请号：US13435210
申请日：2012-03-30
IPC分类号： G05F3/10
CPC分类号： H03K17/102 , H03K3/356113
摘要： A biasing circuit may include an input configured to receive a supply voltage, a value of which is higher than a limit voltage. The biasing circuit may also include a control stage configured to generate first and second control signals with mutually complementary values, equal alternatively to a first value, in a first half-period of a clock signal, or to a second value, in a second half-period of the clock signal. The first and second values may be a function of the supply and limit voltages. The biasing circuit may also include a biasing stage configured to generate a biasing voltage as a function of the values of the first and second control signals. The first and second control signals may control transfer transistors for transferring the supply voltage to respective outputs, while the biasing voltage may be for controlling protection transistors to reduce overvoltages on the transfer transistors.
摘要翻译： 偏置电路可以包括被配置为接收其值高于限制电压的电源电压的输入。 偏置电路还可以包括控制级，其被配置为在时钟信号的第一半个周期中产生第二和第二控制信号，该第一和第二控制信号具有相互互补的值，等于第一个值，或在第二个半个时钟信号中的第二个值 时钟信号的周期。 第一和第二值可以是电源和极限电压的函数。 偏置电路还可以包括被配置为产生作为第一和第二控制信号的值的函数的偏置电压的偏置级。 第一和第二控制信号可以控制用于将电源电压传送到各个输出的转移晶体管，而偏置电压可以用于控制保护晶体管以减小转移晶体管的过电压。
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公开(公告)号：US07742342B2
公开(公告)日：2010-06-22
申请号：US11977876
申请日：2007-10-26
申请人： Antonino Conte , Gianbattista Logiudice , Giovanni Matranga , Mario Micchche' , Carmelo Ucciardello , De Costantini Diego
发明人： Antonino Conte , Gianbattista Logiudice , Giovanni Matranga , Mario Micchche' , Carmelo Ucciardello , De Costantini Diego
IPC分类号： G11C16/06
CPC分类号： G11C16/12
摘要： An EEPROM memory having a matrix of individually selectable memory cells, the matrix having a plurality of columns, a plurality of data lines each coupled with the cells of a corresponding column, the data lines being grouped in a plurality of packets, a plurality of biasing elements for providing a biasing signal to the data lines, and means for selecting the biasing elements for a selected one of the packets, wherein each biasing element is associated with corresponding data lines of a plurality of packets, the biasing element comprising switching means for selectively applying the biasing signal to a selected one of the associated data lines.
摘要翻译： 一种EEPROM存储器，具有单独可选择的存储单元矩阵，该矩阵具有多个列，多个数据线，每条数据线与相应列的单元耦合，数据线被分组成多个分组，多个偏置 用于向数据线提供偏置信号的元件以及用于为所选分组中的所选择的一个分组选择偏置元件的装置，其中每个偏置元件与多个分组的相应数据线相关联，所述偏置元件包括用于选择性地 将偏置信号应用到所选择的一个相关联的数据线。
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公开(公告)号：US08902678B2
公开(公告)日：2014-12-02
申请号：US13405619
申请日：2012-02-27
CPC分类号： G05F1/575 , Y10T29/49117
摘要： A voltage regulator may include an input terminal for receiving an input voltage and an output terminal for providing a respective output voltage, a regulation transistor having a first conduction terminal coupled to the input terminal for receiving the input voltage, a second conduction terminal coupled to the output terminal, and a control terminal coupled to the output of a first operational amplifier. The first operational amplifier may have a non-inverting input terminal for receiving a first reference voltage, and an inverting input terminal coupled to a first terminal of a divider circuit for receiving a second reference voltage.
摘要翻译： 电压调节器可以包括用于接收输入电压的输入端子和用于提供相应输出电压的输出端子;调节晶体管，其具有耦合到输入端子的第一导电端子用于接收输入电压;第二导通端子， 输出端子和耦合到第一运算放大器的输出端的控制端子。 第一运算放大器可以具有用于接收第一参考电压的非反相输入端子，以及耦合到用于接收第二参考电压的除法器电路的第一端子的反相输入端子。
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公开(公告)号：US06535429B2
公开(公告)日：2003-03-18
申请号：US10028747
申请日：2001-12-20
IPC分类号： G11C1606
CPC分类号： G11C16/28
摘要： A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.
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公开(公告)号：US06489831B1
公开(公告)日：2002-12-03
申请号：US09650023
申请日：2000-08-28
IPC分类号： H01L3500
摘要： A CMOS temperature sensor includes a first circuit portion for generating a voltage signal whose value increases with the temperature to be sensed, and a second circuit portion for generating an electric voltage signal whose value decreases with the temperature to be sensed. A comparator is provided as an output stage for comparing the values of both voltage signals. The generator element of the second circuit portion is a vertical bipolar transistor connected in a diode configuration.
摘要翻译： CMOS温度传感器包括：第一电路部分，用于产生其值随着要感测的温度升高的电压信号;以及第二电路部分，用于产生电压信号，该电压信号的值随着要感测的温度而降低。 提供比较器作为用于比较两个电压信号的值的输出级。 第二电路部分的发电机元件是以二极管配置连接的垂直双极晶体管。
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