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1.发明授权Electrically word-erasable non-volatile memory device, and biasing method thereof 有权电可擦除非易失性存储器件及其偏置方法公开(公告)号：US07130219B2
公开(公告)日：2006-10-31
申请号：US11067478
申请日：2005-02-25
IPC分类号： G11C16/04
摘要： A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a plurality of P-type wells extending in a direction transverse to the rows. A plurality of main bitlines extend along the columns. Each P-type well is associated to a set of local bitlines that extend along the respective P-type well and are coupled to the drain terminals of the cells accommodated in the respective P-type well. Local-bitlines managing circuits are provided for each P-type well and are located between the main bitlines and a respective set of local bitlines for controllably connecting each local bitline to a respective main bitline.
摘要翻译： 由存储单元阵列形成的存储器件，其以行和列的形式延伸。 该装置由平行于行的多个N型阱形成; 每个N型井容纳沿横向于行的方向延伸的多个P型井。 多个主位线沿着列延伸。 每个P型阱与沿着相应P型阱延伸的一组本地位线相关联，并且耦合到容纳在相应P型阱中的单元的漏极端子。 为每个P型阱提供局部位线管理电路，并且位于主位线之间，并且位于相应的一组本地位线之间，用于可控地将每个本地位线连接到相应的主位线。
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2.发明申请Electrically word-erasable non-volatile memory device, and biasing method thereof 有权电可擦除非易失性存储器件及其偏置方法公开(公告)号：US20050195654A1
公开(公告)日：2005-09-08
申请号：US11067478
申请日：2005-02-25
摘要： A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a plurality of P-type wells extending in a direction transverse to the rows. A plurality of main bitlines extend along the columns. Each P-type well is associated to a set of local bitlines that extend along the respective P-type well and are coupled to the drain terminals of the cells accommodated in the respective P-type well. Local-bitlines managing circuits are provided for each P-type well and are located between the main bitlines and a respective set of local bitlines for controllably connecting each local bitline to a respective main bitline.
摘要翻译： 由存储单元阵列形成的存储器件，其以行和列的形式延伸。 该装置由平行于行的多个N型阱形成; 每个N型井容纳沿横向于行的方向延伸的多个P型井。 多个主位线沿着列延伸。 每个P型阱与沿着相应P型阱延伸的一组本地位线相关联，并且耦合到容纳在相应P型阱中的单元的漏极端子。 为每个P型阱提供局部位线管理电路，并且位于主位线之间，并且位于相应的一组本地位线之间，用于可控地将每个本地位线连接到相应的主位线。
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公开(公告)号：US07170790B2
公开(公告)日：2007-01-30
申请号：US11061104
申请日：2005-02-18
IPC分类号： G11C16/06
摘要： A sensing circuit (120) for sensing currents, including: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V−); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and a comparison current generating circuit (N3s, 135; N3s, 135′; N3s, 135″) for generating the comparison current based on a reference current (Ir). The comparison current generating circuit includes at least one voltage generator (135; 135′; 135″). A memory device using the sensing circuit and a method are also provided.
摘要翻译： 一种用于感测电流的感测电路（120），包括：测量电路分支（132i），具有用于接收待感测的输入电流（Ic）的测量节点，用于将输入电流转换成对应的输入电压（V- ）; 至少一个比较电路分支（132o），具有用于接收比较电流（Igs）的比较节点，用于将比较电流转换成对应的比较电压（V +）; 以及用于比较输入和比较电压的至少一个电压比较器（140）和用于产生比较电流的比较电流产生电路（N 3 s，135; N 3 s，135'; N 3 s，135“） 基于参考电流（Ir）。 比较电流产生电路包括至少一个电压发生器（135; 135'; 135“）。 还提供了使用感测电路的存储器件和方法。
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公开(公告)号：US20050201169A1
公开(公告)日：2005-09-15
申请号：US11061104
申请日：2005-02-18
摘要： A sensing circuit (120) for sensing currents, including: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V−); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and a comparison current generating circuit (N3s, 135; N3s, 135′; N3s, 135″) for generating the comparison current based on a reference current (Ir). The comparison current generating circuit includes at least one voltage generator (135; 135′; 135″). A memory device using the sensing circuit and a method are also provided.
摘要翻译： 一种用于感测电流的感测电路（120），包括：测量电路分支（132i），具有用于接收待感测的输入电流（Ic）的测量节点，用于将输入电流转换成对应的输入电压（V- ）; 至少一个比较电路分支（132o），具有用于接收比较电流（Igs）的比较节点，用于将比较电流转换成对应的比较电压（V +）; 以及用于比较输入和比较电压的至少一个电压比较器（140）和用于产生比较电流的比较电流产生电路（N 3 s，135; N 3 s，135'; N 3 s，135“） 基于参考电流（Ir）。 比较电流产生电路包括至少一个电压发生器（135; 135'; 135“）。 还提供了使用感测电路的存储器件和方法。
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5.发明授权Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, useful in low supply-voltage technologies 有权用于读取和验证电可编程和可擦除非易失性存储器单元的内容的感测电路，可用于低电源电压技术公开(公告)号：US06906957B2
公开(公告)日：2005-06-14
申请号：US10662151
申请日：2003-09-12
CPC分类号： G11C16/28
摘要： Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.
摘要翻译： 用于读取和验证电可编程和可擦除非易失性存储单元的内容的感测电路包括读出放大器，其具有连接到要读取的单元的第一感测电路部分，并且具有用于连接到第一输入端的第一输入端的输出端 比较器，并具有连接到参考电流发生器的第二参考电路部分，并且具有用于连接到所述比较器的第二输入端子的输出端子，其特征在于，所述第一和所述第二电路部分包括一系列第一和第二 晶体管分别连接在第一参考电压和第二电压基准之间，并且具有连接到所述第一和第二电路部分的所述输出端子的互连互连点。
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公开(公告)号：US08587360B2
公开(公告)日：2013-11-19
申请号：US13435262
申请日：2012-03-30
IPC分类号： H03L5/00
CPC分类号： H03K17/102 , H03K3/356113
摘要： A level-shifter circuit may include a pair of inputs which receive a first and a second low-voltage phase signal having a first voltage dynamic with a first maximum value. The level-shifter circuit may also include a pair of outputs which supply a first high-voltage phase signal and a second high-voltage phase signal, level-shifted with respect to the low-voltage signals and having a second voltage dynamic with a second maximum value, higher than the first maximum value. The level-shifter circuit may further include transfer transistors coupled between one of a first reference terminal and a second reference terminal, which are set at one of a first reference voltage and a second reference voltage, and the first output or second output. Protection elements may be coupled to a respective transfer transistor to protect from overvoltages between at least one of the corresponding conduction terminals and control terminals.
摘要翻译： 电平移动器电路可以包括一对输入，其接收具有第一最大值的具有第一电压动态的第一和第二低电压相位信号。 电平移位器电路还可以包括一对输出，其提供相对于低电压信号电平移位的第一高电压相位信号和第二高电压相位信号，并且具有第二电压动态的第二高电压相位信号 最大值，高于第一个最大值。 电平移位器电路还可以包括耦合在第一参考端子和第二参考端子之一中的传输晶体管，其被设置为第一参考电压和第二参考电压之一以及第一输出或第二输出。 保护元件可以耦合到相应的传输晶体管，以防止在相应的导电端子和控制端子中的至少一个之间的过电压。
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7.发明授权Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, useful in low supply-voltage technologies 有权用于读取和验证电可编程和可擦除非易失性存储器单元的内容的感测电路，可用于低电源电压技术公开(公告)号：US06704233B2
公开(公告)日：2004-03-09
申请号：US10171508
申请日：2002-06-12
IPC分类号： G11C700
CPC分类号： G11C16/28
摘要： Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells including a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.
摘要翻译： 用于读取和验证电可编程和可擦除非易失性存储单元的内容的感测电路，包括读出放大器，该读出放大器具有连接到要读取的单元的第一感测电路部分，并且具有用于连接到第一输入端的输出端 比较器，并且具有连接到参考电流发生器的第二参考电路部分，并且具有用于连接到所述比较器的第二输入端的输出端，其特征在于，所述第一和所述第二电路部分包括一系列第一和第二晶体管 分别连接在第一参考电压和第二电压基准之间，并且具有连接到所述第一和第二电路部分的所述输出端子的互连点。
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8.发明授权Circuit for generating a temperature-compensated voltage reference, in particular for applications with supply voltages lower than 1V 有权用于产生温度补偿电压基准的电路，特别是用于电源电压低于1V的应用公开(公告)号：US08120415B2
公开(公告)日：2012-02-21
申请号：US12464481
申请日：2009-05-12
CPC分类号： G05F3/30
摘要： An embodiment of a circuit is described for the generation of a temperature-compensated voltage reference of the type comprising at least one generator circuit of a band-gap voltage, inserted between a first and a second voltage reference and including an operational amplifier, having in turn a first and a second input terminal connected to an input stage connected to these first and second input terminal and comprising at least one pair of a first and a second bipolar transistor for the generation of a first voltage component proportional to the temperature. The circuit also comprises the control block connected to the generator circuit of a band-gap voltage in correspondence with at least one first control node which is supplied with a biasing voltage value comprising at least one voltage component which increases with the temperature for compensating the variations of the base-emitter voltage of the first and second bipolar transistors and ensure the turn-on of a pair of input transistors of the operational amplifier. The circuit has an output terminal suitable for supplying a temperature-compensated voltage value obtained by the sum of the first voltage component proportional to the temperature and of a second component inversely proportional to the temperature.
摘要翻译： 描述了电路的实施例，用于生成包括插入在第一和第二参考电压之间并包括运算放大器的带隙电压的至少一个发生器电路的类型的温度补偿电压基准，其具有 转动连接到与这些第一和第二输入端连接的输入级的第一和第二输入端，并且包括至少一对第一和第二双极晶体管，用于产生与温度成比例的第一电压分量。 该电路还包括与至少一个第一控制节点相对应的带隙电压连接到发生器电路的控制块，该至少一个第一控制节点被提供有包括至少一个电压分量的偏置电压值，所述至少一个电压分量随着用于补偿变化的温度而增加 的第一和第二双极晶体管的基极 - 发射极电压，并确保运算放大器的一对输入晶体管的导通。 电路具有适于提供通过与温度成比例的第一电压分量和与温度成反比的第二分量的和获得的温度补偿电压值的输出端子。
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9.发明授权公开(公告)号：US07576591B2
公开(公告)日：2009-08-18
申请号：US11780206
申请日：2007-07-19
申请人： Antonino Conte , Carmelo Ucciardello , Carmine D'Alessandro , Mario Micciche , Giovanni Matranga , Diego De Costantini
发明人： Antonino Conte , Carmelo Ucciardello , Carmine D'Alessandro , Mario Micciche , Giovanni Matranga , Diego De Costantini
IPC分类号： G05F1/10
摘要： A charge pump system is provided that includes at least one first pump for generating a first working voltage, a second pump for generating a second working voltage, and a third pump for generating a third working voltage. The first pump is connected to an internal supply voltage reference that can having a limited value, and has an output terminal connected to the second and third pumps so as to supplying them with the first working voltage as their supply voltage. A method is also provided for managing the generation of voltages to be used with such a charge pump system.
摘要翻译： 提供一种电荷泵系统，其包括用于产生第一工作电压的至少一个第一泵，用于产生第二工作电压的第二泵和用于产生第三工作电压的第三泵。 第一泵连接到可以具有有限值的内部电源参考电压，并且具有连接到第二和第三泵的输出端，以便向它们提供第一工作电压作为它们的电源电压。 还提供了一种用于管理与这种电荷泵系统一起使用的电压的产生的方法。
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10.发明申请SENSE-AMPLIFIER CIRCUIT FOR NON-VOLATILE MEMORIES THAT OPERATES AT LOW SUPPLY VOLTAGES 有权用于低电压下运行的非易失性存储器的感应放大器电路公开(公告)号：US20110069554A1
公开(公告)日：2011-03-24
申请号：US12883072
申请日：2010-09-15
IPC分类号： G11C16/06
摘要： A sense-amplifier circuit includes: a comparison stage that compares a cell current that flows in a memory cell and through an associated bitline, with a reference current, for supplying an output signal indicating the state of the memory cell; and a precharging stage, which supplies, during a precharging step prior to the comparison step, a precharging current to the bitline so as to charge a capacitance thereof. The comparison stage includes a first comparison transistor and by a second comparison transistor, which are coupled in current-mirror configuration respectively to a first differential output and to a second differential output, through which a biasing current flows. The precharging stage diverts, during the precharging step, the biasing current towards the bitline as precharging current, and allows, during the comparison step, passage of part of the biasing current towards the first differential output, enabling operation of the current mirror.
摘要翻译： 感测放大器电路包括：比较级，其将存储单元中流动的单元电流和相关联的位线与参考电流进行比较，用于提供指示存储单元的状态的输出信号; 以及预充电阶段，其在比较步骤之前的预充电步骤期间向位线提供预充电电流以对其电容充电。 比较级包括第一比较晶体管和第二比较晶体管，其以电流镜配置分别耦合到第一差分输出和偏置电流流过的第二差分输出。 预充电阶段在预充电步骤期间将作为预充电电流的朝向位线的偏置电流转移，并且在比较步骤期间允许偏置电流的一部分朝向第一差分输出通过，使得能够操作电流镜。
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