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    Memory Calibration During Boot
    1.
    发明申请
    Memory Calibration During Boot 有权

    公开(公告)号：US20210183414A1

    公开(公告)日：2021-06-17

    申请号：US16716616

    申请日：2019-12-17

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Alma L. Juarez Dominguez

    IPC: G11C5/14 ,  G06F11/07 ,  G06F3/06

    Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

    FILTERING MEMORY CALIBRATION
    2.
    发明申请
    FILTERING MEMORY CALIBRATION 审中-公开

    公开(公告)号：US20200285406A1

    公开(公告)日：2020-09-10

    申请号：US16293398

    申请日：2019-03-05

    Applicant: Apple Inc.

    Inventor： Rakesh L. Notani ,  Robert E. Jeter ,  Suhas Kumar Suvarna Ramesh ,  Naveen Kumar Korada ,  Mohammad Rizwan ,  Alma L. Juarez Dominguez ,  John H. Kelm ,  Matthew R. Johnson

    IPC: G06F3/06 ,  G11C11/4063 ,  G11C7/22

    Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.

    Memory Calibration During Boot
    5.
    发明申请
    Memory Calibration During Boot 有权

    公开(公告)号：US20230115215A1

    公开(公告)日：2023-04-13

    申请号：US18054056

    申请日：2022-11-09

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Alma L. Juarez Dominguez

    IPC: G11C5/14 ,  G06F11/07 ,  G06F3/06

    Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

    Memory channels calibration during boot wherein channels are calibrated in parallel based on identifers
    6.
    发明授权
    Memory channels calibration during boot wherein channels are calibrated in parallel based on identifers 有权

    公开(公告)号：US11527269B2

    公开(公告)日：2022-12-13

    申请号：US16716616

    申请日：2019-12-17

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Alma L. Juarez Dominguez

    IPC: G11C5/14 ,  G06F11/07 ,  G06F3/06

    Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

    Filtering memory calibration
    7.
    发明授权
    Filtering memory calibration 有权

    公开(公告)号：US11226752B2

    公开(公告)日：2022-01-18

    申请号：US16293398

    申请日：2019-03-05

    Applicant: Apple Inc.

    Inventor： Rakesh L. Notani ,  Robert E. Jeter ,  Suhas Kumar Suvarna Ramesh ,  Naveen Kumar Korada ,  Mohammad Rizwan ,  Alma L. Juarez Dominguez ,  John H. Kelm ,  Matthew R. Johnson

    IPC: G06F3/06 ,  G11C7/22 ,  G11C11/4063 ,  G11C7/10

    Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.

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