公开(公告)号：US11226752B2

公开(公告)日：2022-01-18

申请号：US16293398

申请日：2019-03-05

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Robert E. Jeter ,  Suhas Kumar Suvarna Ramesh ,  Naveen Kumar Korada ,  Mohammad Rizwan ,  Alma L. Juarez Dominguez ,  John H. Kelm ,  Matthew R. Johnson

IPC: G06F3/06 ,  G11C7/22 ,  G11C11/4063 ,  G11C7/10

Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.

公开(公告)号：US11217285B1

公开(公告)日：2022-01-04

申请号：US16986116

申请日：2020-08-05

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan ,  Naveen Kumar Korada

IPC: G11C7/22 ,  G11C7/10 ,  G06F11/10

Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

公开(公告)号：US20240062792A1

公开(公告)日：2024-02-22

申请号：US18455385

申请日：2023-08-24

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan ,  Naveen Kumar Korada

IPC: G11C7/22 ,  G06F11/10 ,  G11C7/10

CPC classification number: G11C7/22 ,  G06F11/1076 ,  G11C7/10 ,  G11C2207/2254

Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibration, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

公开(公告)号：US11776597B2

公开(公告)日：2023-10-03

申请号：US17646741

申请日：2022-01-03

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan ,  Naveen Kumar Korada

IPC: G11C7/22 ,  G06F11/10 ,  G11C7/10

CPC classification number: G11C7/22 ,  G06F11/1076 ,  G11C7/10 ,  G11C2207/2254

Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

公开(公告)号：US20240078029A1

公开(公告)日：2024-03-07

申请号：US17929212

申请日：2022-09-01

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Jingkui Zheng ,  Ritesh J. Shah ,  Veera Chockalingam ,  Naveen Kumar Korada

IPC: G06F3/06 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G06F3/0632 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0673 ,  G11C11/4076 ,  G11C11/4096

Abstract: Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.

公开(公告)号：US20200285406A1

公开(公告)日：2020-09-10

申请号：US16293398

申请日：2019-03-05

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Robert E. Jeter ,  Suhas Kumar Suvarna Ramesh ,  Naveen Kumar Korada ,  Mohammad Rizwan ,  Alma L. Juarez Dominguez ,  John H. Kelm ,  Matthew R. Johnson

IPC: G06F3/06 ,  G11C11/4063 ,  G11C7/22

Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.

公开(公告)号：US20240295976A1

公开(公告)日：2024-09-05

申请号：US18658740

申请日：2024-05-08

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Jingkui Zheng ,  Ritesh J. Shah ,  Veera Chockalingam ,  Naveen Kumar Korada

IPC: G06F3/06 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/50

CPC classification number: G06F3/0632 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0673 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/50

Abstract: Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.

公开(公告)号：US12014060B2

公开(公告)日：2024-06-18

申请号：US17929212

申请日：2022-09-01

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Jingkui Zheng ,  Ritesh J. Shah ,  Veera Chockalingam ,  Naveen Kumar Korada

IPC: G11C29/00 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/50

CPC classification number: G06F3/0632 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0673 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/50

Abstract: Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.

公开(公告)号：US20220189519A1

公开(公告)日：2022-06-16

申请号：US17646741

申请日：2022-01-03

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan ,  Naveen Kumar Korada

IPC: G11C7/22 ,  G06F11/10 ,  G11C7/10

Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.